Intel® Microarchitecture Code Named Broadwell Events

This section provides reference for hardware events that can be monitored for the CPU(s):

  • 5th generation Intel® Core™ processor family
  • Intel® Microarchitecture Code Named Broadwell
  • EventName Description
    ARITH.FPU_DIV_ACTIVE This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.
    BACLEARS.ANY Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
    BR_INST_EXEC.ALL_BRANCHES This event counts both taken and not taken speculative and retired branch instructions.
    BR_INST_EXEC.ALL_CONDITIONAL This event counts both taken and not taken speculative and retired macro-conditional branch instructions.
    BR_INST_EXEC.ALL_DIRECT_JMP This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.
    BR_INST_EXEC.ALL_DIRECT_NEAR_CALL This event counts both taken and not taken speculative and retired direct near calls.
    BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.
    BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.
    BR_INST_EXEC.NONTAKEN_CONDITIONAL This event counts not taken macro-conditional branch instructions.
    BR_INST_EXEC.TAKEN_CONDITIONAL This event counts taken speculative and retired macro-conditional branch instructions.
    BR_INST_EXEC.TAKEN_DIRECT_JUMP This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.
    BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL This event counts taken speculative and retired direct near calls.
    BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET This event counts taken speculative and retired indirect branches excluding calls and return branches.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL This event counts taken speculative and retired indirect calls including both register and memory indirect.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN This event counts taken speculative and retired indirect branches that have a return mnemonic.
    BR_INST_RETIRED.ALL_BRANCHES This event counts all (macro) branch instructions retired.
    BR_INST_RETIRED.ALL_BRANCHES_PS This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.
    BR_INST_RETIRED.CONDITIONAL This event counts conditional branch instructions retired.
    BR_INST_RETIRED.CONDITIONAL_PS This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.
    BR_INST_RETIRED.FAR_BRANCH This event counts far branch instructions retired.
    BR_INST_RETIRED.NEAR_CALL This event counts both direct and indirect near call instructions retired.
    BR_INST_RETIRED.NEAR_CALL_PS This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.
    BR_INST_RETIRED.NEAR_CALL_R3 This event counts both direct and indirect macro near call instructions retired (captured in ring 3).
    BR_INST_RETIRED.NEAR_CALL_R3_PS This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).
    BR_INST_RETIRED.NEAR_RETURN This event counts return instructions retired.
    BR_INST_RETIRED.NEAR_RETURN_PS This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.
    BR_INST_RETIRED.NEAR_TAKEN This event counts taken branch instructions retired.
    BR_INST_RETIRED.NEAR_TAKEN_PS This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.
    BR_INST_RETIRED.NOT_TAKEN This event counts not taken branch instructions retired.
    BR_MISP_EXEC.ALL_BRANCHES This event counts both taken and not taken speculative and retired mispredicted branch instructions.
    BR_MISP_EXEC.ALL_CONDITIONAL This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.
    BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.NONTAKEN_CONDITIONAL This event counts not taken speculative and retired mispredicted macro conditional branch instructions.
    BR_MISP_EXEC.TAKEN_CONDITIONAL This event counts taken speculative and retired mispredicted macro conditional branch instructions.
    BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired mispredicted indirect calls.
    BR_MISP_EXEC.TAKEN_RETURN_NEAR This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.
    BR_MISP_RETIRED.ALL_BRANCHES This event counts all mispredicted macro branch instructions retired.
    BR_MISP_RETIRED.ALL_BRANCHES_PS This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.
    BR_MISP_RETIRED.CONDITIONAL This event counts mispredicted conditional branch instructions retired.
    BR_MISP_RETIRED.CONDITIONAL_PS This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.
    BR_MISP_RETIRED.NEAR_TAKEN Number of near branch instructions retired that were mispredicted and taken.
    BR_MISP_RETIRED.NEAR_TAKEN_PS Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).
    BR_MISP_RETIRED.RET This event counts mispredicted return instructions retired.
    BR_MISP_RETIRED.RET_PS This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.
    CPL_CYCLES.RING0 This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.
    CPL_CYCLES.RING0_TRANS This event counts when there is a transition from ring 1,2 or 3 to ring0.
    CPL_CYCLES.RING123 This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.
    CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other thread is halted.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
    CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other thread is halted.
    CPU_CLK_UNHALTED.REF_TSC This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.
    CPU_CLK_UNHALTED.REF_XCLK Reference cycles when the thread is unhalted (counts at 100 MHz rate).
    CPU_CLK_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
    CPU_CLK_UNHALTED.THREAD This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
    CPU_CLK_UNHALTED.THREAD_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CPU_CLK_UNHALTED.THREAD_P This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.
    CPU_CLK_UNHALTED.THREAD_P_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.CYCLES_L1D_PENDING Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.
    CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.CYCLES_L2_PENDING Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.
    CYCLE_ACTIVITY.CYCLES_LDM_PENDING Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).
    CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an outstanding load.
    CYCLE_ACTIVITY.CYCLES_NO_EXECUTE Counts number of cycles nothing is executed on any execution port.
    CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.STALLS_L1D_PENDING Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.
    CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.STALLS_L2_PENDING Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.
    CYCLE_ACTIVITY.STALLS_LDM_PENDING Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.
    CYCLE_ACTIVITY.STALLS_MEM_ANY Execution stalls while memory subsystem has an outstanding load.
    CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls.
    DSB2MITE_SWITCHES.PENALTY_CYCLES This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles.
    DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).
    DTLB_LOAD_MISSES.STLB_HIT Load operations that miss the first DTLB level but hit the second and do not cause page walks.
    DTLB_LOAD_MISSES.STLB_HIT_2M Load misses that miss the DTLB and hit the STLB (2M).
    DTLB_LOAD_MISSES.STLB_HIT_4K Load misses that miss the DTLB and hit the STLB (4K).
    DTLB_LOAD_MISSES.WALK_COMPLETED Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
    DTLB_LOAD_MISSES.WALK_COMPLETED_1G This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.
    DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.
    DTLB_LOAD_MISSES.WALK_COMPLETED_4K This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.
    DTLB_LOAD_MISSES.WALK_DURATION This event counts the number of cycles while PMH is busy with the page walk.
    DTLB_STORE_MISSES.MISS_CAUSES_A_WALK This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).
    DTLB_STORE_MISSES.STLB_HIT Store operations that miss the first TLB level but hit the second and do not cause page walks.
    DTLB_STORE_MISSES.STLB_HIT_2M Store misses that miss the DTLB and hit the STLB (2M).
    DTLB_STORE_MISSES.STLB_HIT_4K Store misses that miss the DTLB and hit the STLB (4K).
    DTLB_STORE_MISSES.WALK_COMPLETED Store misses in all DTLB levels that cause completed page walks.
    DTLB_STORE_MISSES.WALK_COMPLETED_1G This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.
    DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.
    DTLB_STORE_MISSES.WALK_COMPLETED_4K This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.
    DTLB_STORE_MISSES.WALK_DURATION This event counts the number of cycles while PMH is busy with the page walk.
    EPT.WALK_CYCLES This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.
    FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.DOUBLE Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.
    FP_ARITH_INST_RETIRED.PACKED Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.SCALAR Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.SCALAR_DOUBLE Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.SCALAR_SINGLE Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
    FP_ARITH_INST_RETIRED.SINGLE Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.
    FP_ASSIST.ANY This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.
    FP_ASSIST.SIMD_INPUT This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.
    FP_ASSIST.SIMD_OUTPUT This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.
    FP_ASSIST.X87_INPUT This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.
    FP_ASSIST.X87_OUTPUT This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.
    HLE_RETIRED.ABORTED Number of times HLE abort was triggered.
    HLE_RETIRED.ABORTED_MISC1 Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).
    HLE_RETIRED.ABORTED_MISC2 Number of times the TSX watchdog signaled an HLE abort.
    HLE_RETIRED.ABORTED_MISC3 Number of times a disallowed operation caused an HLE abort.
    HLE_RETIRED.ABORTED_MISC4 Number of times HLE caused a fault.
    HLE_RETIRED.ABORTED_MISC5 Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.
    HLE_RETIRED.ABORTED_PS Number of times HLE abort was triggered (PEBS).
    HLE_RETIRED.COMMIT Number of times HLE commit succeeded.
    HLE_RETIRED.START Number of times we entered an HLE region does not count nested transactions.
    ICACHE.HIT This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.
    ICACHE.IFDATA_STALL This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).
    ICACHE.MISSES This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.
    IDQ.ALL_DSB_CYCLES_4_UOPS This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.
    IDQ.ALL_DSB_CYCLES_ANY_UOPS This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.
    IDQ.ALL_MITE_CYCLES_4_UOPS This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
    IDQ.ALL_MITE_CYCLES_ANY_UOPS This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
    IDQ.DSB_CYCLES This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.
    IDQ.DSB_UOPS This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.
    IDQ.EMPTY This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.
    IDQ.MITE_ALL_UOPS This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
    IDQ.MITE_CYCLES This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ.
    IDQ.MITE_UOPS This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
    IDQ.MS_CYCLES This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.
    IDQ.MS_DSB_CYCLES This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.
    IDQ.MS_DSB_OCCUR This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.
    IDQ.MS_DSB_UOPS This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.
    IDQ.MS_MITE_UOPS This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ.
    IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
    IDQ.MS_UOPS This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.
    IDQ_UOPS_NOT_DELIVERED.CORE This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE Cycles with less than 2 uops delivered by the front end.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE Cycles with less than 3 uops delivered by the front end.
    ILD_STALL.LCP This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.
    INST_RETIRED.ANY This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.
    INST_RETIRED.ANY_P This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).
    INST_RETIRED.PREC_DIST This is a precise version (that is, uses PEBS) of the event that counts instructions retired.
    INST_RETIRED.X87 This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.
    INT_MISC.RAT_STALL_CYCLES This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.
    INT_MISC.RECOVERY_CYCLES Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.
    INT_MISC.RECOVERY_CYCLES_ANY Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
    ITLB.ITLB_FLUSH This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).
    ITLB_MISSES.MISS_CAUSES_A_WALK This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).
    ITLB_MISSES.STLB_HIT Operations that miss the first ITLB level but hit the second and do not cause any page walks.
    ITLB_MISSES.STLB_HIT_2M Code misses that miss the DTLB and hit the STLB (2M).
    ITLB_MISSES.STLB_HIT_4K Core misses that miss the DTLB and hit the STLB (4K).
    ITLB_MISSES.WALK_COMPLETED Misses in all ITLB levels that cause completed page walks.
    ITLB_MISSES.WALK_COMPLETED_1G This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.
    ITLB_MISSES.WALK_COMPLETED_2M_4M This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.
    ITLB_MISSES.WALK_COMPLETED_4K This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.
    ITLB_MISSES.WALK_DURATION This event counts the number of cycles while PMH is busy with the page walk.
    L1D.REPLACEMENT This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.
    L1D_PEND_MISS.FB_FULL Cycles a demand request was blocked due to Fill Buffers inavailability.
    L1D_PEND_MISS.PENDING This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.
    L1D_PEND_MISS.PENDING_CYCLES This event counts duration of L1D miss outstanding in cycles.
    L1D_PEND_MISS.PENDING_CYCLES_ANY Cycles with L1D load Misses outstanding from any thread on physical core.
    L2_DEMAND_RQSTS.WB_HIT This event counts the number of WB requests that hit L2 cache.
    L2_LINES_IN.ALL This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.
    L2_LINES_IN.E This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.
    L2_LINES_IN.I This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.
    L2_LINES_IN.S This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.
    L2_LINES_OUT.DEMAND_CLEAN Clean L2 cache lines evicted by demand.
    L2_RQSTS.ALL_CODE_RD This event counts the total number of L2 code requests.
    L2_RQSTS.ALL_DEMAND_DATA_RD This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.
    L2_RQSTS.ALL_DEMAND_MISS Demand requests that miss L2 cache.
    L2_RQSTS.ALL_DEMAND_REFERENCES Demand requests to L2 cache.
    L2_RQSTS.ALL_PF This event counts the total number of requests from the L2 hardware prefetchers.
    L2_RQSTS.ALL_RFO This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
    L2_RQSTS.CODE_RD_HIT L2 cache hits when fetching instructions, code reads.
    L2_RQSTS.CODE_RD_MISS L2 cache misses when fetching instructions.
    L2_RQSTS.DEMAND_DATA_RD_HIT This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.
    L2_RQSTS.DEMAND_DATA_RD_MISS This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.
    L2_RQSTS.L2_PF_HIT This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.
    L2_RQSTS.L2_PF_MISS This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.
    L2_RQSTS.MISS All requests that miss L2 cache.
    L2_RQSTS.REFERENCES All L2 requests.
    L2_RQSTS.RFO_HIT RFO requests that hit L2 cache.
    L2_RQSTS.RFO_MISS RFO requests that miss L2 cache.
    L2_TRANS.ALL_PF This event counts L2 or L3 HW prefetches that access L2 cache including rejects.
    L2_TRANS.ALL_REQUESTS This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.
    L2_TRANS.CODE_RD This event counts the number of L2 cache accesses when fetching instructions.
    L2_TRANS.DEMAND_DATA_RD This event counts Demand Data Read requests that access L2 cache, including rejects.
    L2_TRANS.L1D_WB This event counts L1D writebacks that access L2 cache.
    L2_TRANS.L2_FILL This event counts L2 fill requests that access L2 cache.
    L2_TRANS.L2_WB This event counts L2 writebacks that access L2 cache.
    L2_TRANS.RFO This event counts Read for Ownership (RFO) requests that access L2 cache.
    LD_BLOCKS.NO_SR This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
    LD_BLOCKS.STORE_FORWARD This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.
    LD_BLOCKS_PARTIAL.ADDRESS_ALIAS This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.
    LOAD_HIT_PRE.HW_PF This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.
    LOAD_HIT_PRE.SW_PF This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.
    LOCK_CYCLES.CACHE_LOCK_DURATION This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).
    LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.
    LONGEST_LAT_CACHE.MISS This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.
    LONGEST_LAT_CACHE.REFERENCE This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.
    LSD.CYCLES_4_UOPS Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
    LSD.CYCLES_ACTIVE Cycles Uops delivered by the LSD, but didn't come from the decoder.
    LSD.UOPS Number of Uops delivered by the LSD.
    MACHINE_CLEARS.COUNT Number of machine clears (nukes) of any type.
    MACHINE_CLEARS.CYCLES This event counts both thread-specific (TS) and all-thread (AT) nukes.
    MACHINE_CLEARS.MASKMOV Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.
    MACHINE_CLEARS.MEMORY_ORDERING This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer.
    MACHINE_CLEARS.SMC This event counts self-modifying code (SMC) detected, which causes a machine clear.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.
    MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.
    MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).
    MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.
    MEM_LOAD_UOPS_RETIRED.HIT_LFB This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.
    MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.
    MEM_LOAD_UOPS_RETIRED.L1_HIT This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.
    MEM_LOAD_UOPS_RETIRED.L1_HIT_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.
    MEM_LOAD_UOPS_RETIRED.L1_MISS This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.
    MEM_LOAD_UOPS_RETIRED.L1_MISS_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.
    MEM_LOAD_UOPS_RETIRED.L2_HIT This event counts retired load uops which data sources were hits in the mid-level (L2) cache.
    MEM_LOAD_UOPS_RETIRED.L2_HIT_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.
    MEM_LOAD_UOPS_RETIRED.L2_MISS This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.
    MEM_LOAD_UOPS_RETIRED.L2_MISS_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.
    MEM_LOAD_UOPS_RETIRED.L3_HIT This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.
    MEM_LOAD_UOPS_RETIRED.L3_HIT_PS This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.
    MEM_LOAD_UOPS_RETIRED.L3_MISS Miss in last-level (L3) cache. Excludes Unknown data-source.
    MEM_LOAD_UOPS_RETIRED.L3_MISS_PS Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 This event counts loads with latency value being above 128.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 This event counts loads with latency value being above 16.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 This event counts loads with latency value being above 256.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 This event counts loads with latency value being above 32.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 This event counts loads with latency value being above four.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 This event counts loads with latency value being above 512.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 This event counts loads with latency value being above 64.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 This event counts loads with latency value being above eight.
    MEM_UOPS_RETIRED.ALL_LOADS This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.
    MEM_UOPS_RETIRED.ALL_LOADS_PS This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.
    MEM_UOPS_RETIRED.ALL_STORES This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.
    MEM_UOPS_RETIRED.ALL_STORES_PS This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.
    MEM_UOPS_RETIRED.LOCK_LOADS This event counts load uops with locked access retired to the architected path.
    MEM_UOPS_RETIRED.LOCK_LOADS_PS This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.
    MEM_UOPS_RETIRED.SPLIT_LOADS This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.SPLIT_LOADS_PS This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.SPLIT_STORES This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.SPLIT_STORES_PS This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.STLB_MISS_LOADS This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
    MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
    MEM_UOPS_RETIRED.STLB_MISS_STORES This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
    MEM_UOPS_RETIRED.STLB_MISS_STORES_PS This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
    MISALIGN_MEM_REF.LOADS This event counts speculative cache-line split load uops dispatched to the L1 cache.
    MISALIGN_MEM_REF.STORES This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.
    MOVE_ELIMINATION.INT_ELIMINATED Number of integer Move Elimination candidate uops that were eliminated.
    MOVE_ELIMINATION.INT_NOT_ELIMINATED Number of integer Move Elimination candidate uops that were not eliminated.
    MOVE_ELIMINATION.SIMD_ELIMINATED Number of SIMD Move Elimination candidate uops that were eliminated.
    MOVE_ELIMINATION.SIMD_NOT_ELIMINATED Number of SIMD Move Elimination candidate uops that were not eliminated.
    OFFCORE_REQUESTS.ALL_DATA_RD This event counts the demand and prefetch data reads. All Core Data Reads include cacheable "Demands" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.
    OFFCORE_REQUESTS.DEMAND_CODE_RD This event counts both cacheable and noncachaeble code read requests.
    OFFCORE_REQUESTS.DEMAND_DATA_RD This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.
    OFFCORE_REQUESTS.DEMAND_RFO This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.
    OFFCORE_REQUESTS_BUFFER.SQ_FULL This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries.
    OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.
    OFFCORE_RESPONSE Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.
    OTHER_ASSISTS.ANY_WB_ASSIST Number of times any microcode assist is invoked by HW upon uop writeback.
    OTHER_ASSISTS.AVX_TO_SSE This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.
    OTHER_ASSISTS.SSE_TO_AVX This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.
    PAGE_WALKER_LOADS.DTLB_L1 Number of DTLB page walker hits in the L1+FB.
    PAGE_WALKER_LOADS.DTLB_L2 Number of DTLB page walker hits in the L2.
    PAGE_WALKER_LOADS.DTLB_L3 Number of DTLB page walker hits in the L3 + XSNP.
    PAGE_WALKER_LOADS.DTLB_MEMORY Number of DTLB page walker hits in Memory.
    PAGE_WALKER_LOADS.ITLB_L1 Number of ITLB page walker hits in the L1+FB.
    PAGE_WALKER_LOADS.ITLB_L2 Number of ITLB page walker hits in the L2.
    PAGE_WALKER_LOADS.ITLB_L3 Number of ITLB page walker hits in the L3 + XSNP.
    RESOURCE_STALLS.ANY This event counts resource-related stall cycles. Reasons for stalls can be as follows: - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots) - *any* u-arch structure got empty (like INT/SIMD FreeLists) - FPU control word (FPCW), MXCSR and others. This counts cycles that the pipeline backend blocked uop delivery from the front end.
    RESOURCE_STALLS.ROB This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.
    RESOURCE_STALLS.RS This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.
    RESOURCE_STALLS.SB This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.
    ROB_MISC_EVENTS.LBR_INSERTS This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.
    RS_EVENTS.EMPTY_CYCLES This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.
    RS_EVENTS.EMPTY_END Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
    RTM_RETIRED.ABORTED Number of times RTM abort was triggered .
    RTM_RETIRED.ABORTED_MISC1 Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).
    RTM_RETIRED.ABORTED_MISC2 Number of times the TSX watchdog signaled an RTM abort.
    RTM_RETIRED.ABORTED_MISC3 Number of times a disallowed operation caused an RTM abort.
    RTM_RETIRED.ABORTED_MISC4 Number of times a RTM caused a fault.
    RTM_RETIRED.ABORTED_MISC5 Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.
    RTM_RETIRED.ABORTED_PS Number of times RTM abort was triggered (PEBS).
    RTM_RETIRED.COMMIT Number of times RTM commit succeeded.
    RTM_RETIRED.START Number of times we entered an RTM region does not count nested transactions.
    SQ_MISC.SPLIT_LOCK This event counts the number of split locks in the super queue.
    TLB_FLUSH.DTLB_THREAD This event counts the number of DTLB flush attempts of the thread-specific entries.
    TLB_FLUSH.STLB_ANY This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).
    TX_EXEC.MISC1 Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.
    TX_EXEC.MISC2 Unfriendly TSX abort triggered by a vzeroupper instruction.
    TX_EXEC.MISC3 Unfriendly TSX abort triggered by a nest count that is too deep.
    TX_EXEC.MISC4 RTM region detected inside HLE.
    TX_EXEC.MISC5 Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.
    TX_MEM.ABORT_CAPACITY_WRITE Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.
    TX_MEM.ABORT_CONFLICT Number of times a TSX line had a cache conflict.
    TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.
    TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.
    TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.
    TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK Number of times a TSX Abort was triggered due to a non-release/commit store to lock.
    TX_MEM.HLE_ELISION_BUFFER_FULL Number of times we could not allocate Lock Buffer.
    UOP_DISPATCHES_CANCELLED.SIMD_PRF This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.
    UOPS_DISPATCHED_PORT.PORT_0 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.
    UOPS_DISPATCHED_PORT.PORT_1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.
    UOPS_DISPATCHED_PORT.PORT_2 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.
    UOPS_DISPATCHED_PORT.PORT_3 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.
    UOPS_DISPATCHED_PORT.PORT_4 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.
    UOPS_DISPATCHED_PORT.PORT_5 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.
    UOPS_DISPATCHED_PORT.PORT_6 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.
    UOPS_DISPATCHED_PORT.PORT_7 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
    UOPS_EXECUTED.CORE Number of uops executed from any thread.
    UOPS_EXECUTED.CORE_CYCLES_GE_1 Cycles at least 1 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_2 Cycles at least 2 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_3 Cycles at least 3 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_4 Cycles at least 4 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_NONE Cycles with no micro-ops executed from any thread on physical core.
    UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC Cycles where at least 1 uop was executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC Cycles where at least 2 uops were executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC Cycles where at least 3 uops were executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC Cycles where at least 4 uops were executed per-thread.
    UOPS_EXECUTED.STALL_CYCLES This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.
    UOPS_EXECUTED.THREAD Number of uops to be executed per-thread each cycle.
    UOPS_EXECUTED_PORT.PORT_0 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.
    UOPS_EXECUTED_PORT.PORT_0_CORE Cycles per core when uops are exectuted in port 0.
    UOPS_EXECUTED_PORT.PORT_1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.
    UOPS_EXECUTED_PORT.PORT_1_CORE Cycles per core when uops are exectuted in port 1.
    UOPS_EXECUTED_PORT.PORT_2 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.
    UOPS_EXECUTED_PORT.PORT_2_CORE Cycles per core when uops are dispatched to port 2.
    UOPS_EXECUTED_PORT.PORT_3 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.
    UOPS_EXECUTED_PORT.PORT_3_CORE Cycles per core when uops are dispatched to port 3.
    UOPS_EXECUTED_PORT.PORT_4 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.
    UOPS_EXECUTED_PORT.PORT_4_CORE Cycles per core when uops are exectuted in port 4.
    UOPS_EXECUTED_PORT.PORT_5 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.
    UOPS_EXECUTED_PORT.PORT_5_CORE Cycles per core when uops are exectuted in port 5.
    UOPS_EXECUTED_PORT.PORT_6 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.
    UOPS_EXECUTED_PORT.PORT_6_CORE Cycles per core when uops are exectuted in port 6.
    UOPS_EXECUTED_PORT.PORT_7 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
    UOPS_EXECUTED_PORT.PORT_7_CORE Cycles per core when uops are dispatched to port 7.
    UOPS_ISSUED.ANY This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).
    UOPS_ISSUED.FLAGS_MERGE Number of flags-merge uops being allocated. Such uops considered perf sensitive added by GSR u-arch.
    UOPS_ISSUED.SINGLE_MUL Number of Multiply packed/scalar single precision uops allocated.
    UOPS_ISSUED.SLOW_LEA Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
    UOPS_ISSUED.STALL_CYCLES This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.
    UOPS_RETIRED.ALL This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.
    UOPS_RETIRED.ALL_PS This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.
    UOPS_RETIRED.RETIRE_SLOTS This event counts the number of retirement slots used.
    UOPS_RETIRED.RETIRE_SLOTS_PS This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.
    UOPS_RETIRED.STALL_CYCLES This event counts cycles without actually retired uops.
    UOPS_RETIRED.TOTAL_CYCLES Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.
    UNC_ARB_COH_TRK_REQUESTS.ALL Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.
    UNC_ARB_TRK_OCCUPANCY.ALL Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.
    UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
    UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT Each cycle count number of "valid" coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.
    UNC_ARB_TRK_REQUESTS.ALL Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.
    UNC_ARB_TRK_REQUESTS.DRD_DIRECT Number of Core coherent Data Read entries allocated in DirectData mode.
    UNC_ARB_TRK_REQUESTS.WRITES Number of Writes allocated - any write transactions: full/partials writes and evictions.
    UNC_CBO_CACHE_LOOKUP.ANY_ES L3 Lookup any request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.ANY_I L3 Lookup any request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.ANY_M L3 Lookup any request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.ANY_MESI L3 Lookup any request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.READ_ES L3 Lookup read request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.READ_I L3 Lookup read request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.READ_M L3 Lookup read request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.READ_MESI L3 Lookup read request that access cache and found line in any MESI-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_ES L3 Lookup write request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_M L3 Lookup write request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_MESI L3 Lookup write request that access cache and found line in MESI-state.
    UNC_CBO_XSNP_RESPONSE.HIT_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_EVICTION A cross-core snoop resulted from L3 Eviction which misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.
    UNC_CLOCK.SOCKET This 48-bit fixed counter counts the UCLK cycles.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=ANY_RESPONSE Counts demand data reads that have any response type.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NONE Counts demand data reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_MISS Counts demand data reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_HITM Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM Counts demand data reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.ANY_SNOOP Counts demand data reads that hit in the L3.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_NONE Counts demand data reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_MISS Counts demand data reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts demand data reads
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=ANY_RESPONSE Counts all demand data writes (RFOs) that have any response type.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_NONE Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_MISS Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_HITM Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=SUPPLIER_NONE.ANY_SNOOP Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NONE Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NOT_NEEDED Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_MISS Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_HITM Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NON_DRAM Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.ANY_SNOOP Counts all demand data writes (RFOs) that hit in the L3.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_NONE Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_NOT_NEEDED Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_MISS Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all demand data writes (RFOs)
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=ANY_RESPONSE Counts all demand code reads that have any response type.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NONE Counts all demand code reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_MISS Counts all demand code reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_HITM Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all demand code reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.ANY_SNOOP Counts all demand code reads that hit in the L3.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_NONE Counts all demand code reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all demand code reads
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_MISS Counts all demand code reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all demand code reads
    OFFCORE_RESPONSE:request=COREWB: response=ANY_RESPONSE Counts writebacks (modified to exclusive) that have any response type.
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NONE Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_MISS Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_HITM Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.ANY_SNOOP Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NONE Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NOT_NEEDED Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_MISS Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_HIT_NO_FWD Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_HITM Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NON_DRAM Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.ANY_SNOOP Counts writebacks (modified to exclusive) that hit in the L3.
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_NONE Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_NOT_NEEDED Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_MISS Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_HIT_NO_FWD Counts writebacks (modified to exclusive)
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=ANY_RESPONSE Counts prefetch (that bring data to L2) data reads that have any response type.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NONE Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_MISS Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_HITM Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.ANY_SNOOP Counts prefetch (that bring data to L2) data reads that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_NONE Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_MISS Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to L2) data reads
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=ANY_RESPONSE Counts all prefetch (that bring data to L2) RFOs that have any response type.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_HITM Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to L2) RFOs
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=ANY_RESPONSE Counts all prefetch (that bring data to LLC only) code reads that have any response type.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NONE Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_MISS Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_HITM Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.ANY_SNOOP Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_NONE Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_MISS Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=ANY_RESPONSE Counts all prefetch (that bring data to LLC only) data reads that have any response type.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_HITM Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) data reads
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=ANY_RESPONSE Counts all prefetch (that bring data to LLC only) RFOs that have any response type.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_MISS Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_HITM Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_MISS Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=ANY_RESPONSE Counts prefetch (that bring data to LLC only) code reads that have any response type.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NONE Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_MISS Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_HITM Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.ANY_SNOOP Counts prefetch (that bring data to LLC only) code reads that hit in the L3.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_NONE Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_MISS Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts prefetch (that bring data to LLC only) code reads
    OFFCORE_RESPONSE:request=OTHER: response=ANY_RESPONSE Counts any other requests that have any response type.
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NONE Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_MISS Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_HITM Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.ANY_SNOOP Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NONE Counts any other requests that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NOT_NEEDED Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_MISS Counts any other requests that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_HIT_NO_FWD Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_HITM Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NON_DRAM Counts any other requests that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.ANY_SNOOP Counts any other requests that hit in the L3.
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_NONE Counts any other requests that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_NOT_NEEDED Counts any other requests
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_MISS Counts any other requests that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_HIT_NO_FWD Counts any other requests
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=ANY_RESPONSE Counts all prefetch data reads that have any response type.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NONE Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_MISS Counts all prefetch data reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_HITM Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.ANY_SNOOP Counts all prefetch data reads that hit in the L3.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_NONE Counts all prefetch data reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_MISS Counts all prefetch data reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch data reads
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=ANY_RESPONSE Counts prefetch RFOs that have any response type.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NONE Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_MISS Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_HITM Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.ANY_SNOOP Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NONE Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NOT_NEEDED Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_MISS Counts prefetch RFOs that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_HITM Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NON_DRAM Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.ANY_SNOOP Counts prefetch RFOs that hit in the L3.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_NONE Counts prefetch RFOs that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_NOT_NEEDED Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_MISS Counts prefetch RFOs that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD Counts prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=ANY_RESPONSE Counts all prefetch code reads that have any response type.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NONE Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_MISS Counts all prefetch code reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_HITM Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.ANY_SNOOP Counts all prefetch code reads that hit in the L3.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_NONE Counts all prefetch code reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_MISS Counts all prefetch code reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all prefetch code reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=ANY_RESPONSE Counts all demand & prefetch data reads that have any response type.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NONE Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_MISS Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_HITM Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.ANY_SNOOP Counts all demand & prefetch data reads that hit in the L3.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_NONE Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_MISS Counts all demand & prefetch data reads that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all demand & prefetch data reads
    OFFCORE_RESPONSE:request=ALL_RFO: response=ANY_RESPONSE Counts all demand & prefetch RFOs that have any response type.
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NONE Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_MISS Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_HITM Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.ANY_SNOOP Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NONE Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NOT_NEEDED Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_MISS Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_HITM Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NON_DRAM Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.ANY_SNOOP Counts all demand & prefetch RFOs that hit in the L3.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_NONE Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_NOT_NEEDED Counts all demand & prefetch RFOs
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_MISS Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response.
    OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD Counts all demand & prefetch RFOs