Intel® Microarchitecture Code Named Westmere EP-DP Events

This section provides reference for hardware events that can be monitored for the CPU(s):

  • Intel® Xeon® / Core i7 980X processor
  • EventName Description
    ARITH.CYCLES_DIV_BUSY Cycles the divider is busy
    ARITH.DIV Divide Operations executed
    ARITH.MUL Multiply operations executed
    BACLEAR.BAD_TARGET BACLEAR asserted with bad target address
    BACLEAR.CLEAR BACLEAR asserted, regardless of cause
    BACLEAR_FORCE_IQ Instruction queue forced BACLEAR
    BPU_CLEARS.EARLY Early Branch Prediciton Unit clears
    BPU_CLEARS.LATE Late Branch Prediction Unit clears
    BPU_MISSED_CALL_RET Branch prediction unit missed call or return
    BR_INST_DECODED Branch instructions decoded
    BR_INST_EXEC.ANY Branch instructions executed
    BR_INST_EXEC.COND Conditional branch instructions executed
    BR_INST_EXEC.DIRECT Unconditional branches executed
    BR_INST_EXEC.DIRECT_NEAR_CALL Unconditional call branches executed
    BR_INST_EXEC.INDIRECT_NEAR_CALL Indirect call branches executed
    BR_INST_EXEC.INDIRECT_NON_CALL Indirect non call branches executed
    BR_INST_EXEC.NEAR_CALLS Call branches executed
    BR_INST_EXEC.NON_CALLS All non call branches executed
    BR_INST_EXEC.RETURN_NEAR Indirect return branches executed
    BR_INST_EXEC.TAKEN Taken branches executed
    BR_INST_RETIRED.ALL_BRANCHES Retired branch instructions (Precise Event)
    BR_INST_RETIRED.CONDITIONAL Retired conditional branch instructions (Precise Event)
    BR_INST_RETIRED.NEAR_CALL Retired near call instructions (Precise Event)
    BR_INST_RETIRED.NEAR_CALL_R3 Retired near call instructions Ring 3 only(Precise Event)
    BR_MISP_EXEC.ANY Mispredicted branches executed
    BR_MISP_EXEC.COND Mispredicted conditional branches executed
    BR_MISP_EXEC.DIRECT Mispredicted unconditional branches executed
    BR_MISP_EXEC.DIRECT_NEAR_CALL Mispredicted non call branches executed
    BR_MISP_EXEC.INDIRECT_NEAR_CALL Mispredicted indirect call branches executed
    BR_MISP_EXEC.INDIRECT_NON_CALL Mispredicted indirect non call branches executed
    BR_MISP_EXEC.NEAR_CALLS Mispredicted call branches executed
    BR_MISP_EXEC.NON_CALLS Mispredicted non call branches executed
    BR_MISP_EXEC.RETURN_NEAR Mispredicted return branches executed
    BR_MISP_EXEC.TAKEN Mispredicted taken branches executed
    BR_MISP_RETIRED.ALL_BRANCHES Mispredicted retired branch instructions (Precise Event)
    BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional retired branches (Precise Event)
    BR_MISP_RETIRED.NEAR_CALL Mispredicted near retired calls (Precise Event)
    CACHE_LOCK_CYCLES.L1D Cycles L1D locked
    CACHE_LOCK_CYCLES.L1D_L2 Cycles L1D and L2 locked
    CPU_CLK_UNHALTED.REF Reference cycles when thread is not halted (fixed counter)
    CPU_CLK_UNHALTED.REF_P Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
    CPU_CLK_UNHALTED.THREAD Cycles when thread is not halted (fixed counter)
    CPU_CLK_UNHALTED.THREAD_P Cycles when thread is not halted (programmable counter)
    CPU_CLK_UNHALTED.TOTAL_CYCLES Total CPU cycles
    DTLB_LOAD_MISSES.ANY DTLB load misses
    DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED DTLB load miss large page walks
    DTLB_LOAD_MISSES.PDE_MISS DTLB load miss caused by low part of address
    DTLB_LOAD_MISSES.STLB_HIT DTLB second level hit
    DTLB_LOAD_MISSES.WALK_COMPLETED DTLB load miss page walks complete
    DTLB_LOAD_MISSES.WALK_CYCLES DTLB load miss page walk cycles
    DTLB_MISSES.ANY DTLB misses
    DTLB_MISSES.LARGE_WALK_COMPLETED DTLB miss large page walks
    DTLB_MISSES.PDE_MISS DTLB misses casued by low part of address
    DTLB_MISSES.STLB_HIT DTLB first level misses but second level hit
    DTLB_MISSES.WALK_COMPLETED DTLB miss page walks
    DTLB_MISSES.WALK_CYCLES DTLB miss page walk cycles
    EPT.WALK_CYCLES Extended Page Table walk cycles
    ES_REG_RENAMES ES segment renames
    FP_ASSIST.ALL X87 Floating point assists (Precise Event)
    FP_ASSIST.INPUT X87 Floating poiint assists for invalid input value (Precise Event)
    FP_ASSIST.OUTPUT X87 Floating point assists for invalid output value (Precise Event)
    FP_COMP_OPS_EXE.MMX MMX Uops
    FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION SSE* FP double precision Uops
    FP_COMP_OPS_EXE.SSE_FP SSE and SSE2 FP Uops
    FP_COMP_OPS_EXE.SSE_FP_PACKED SSE FP packed Uops
    FP_COMP_OPS_EXE.SSE_FP_SCALAR SSE FP scalar Uops
    FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION SSE* FP single precision Uops
    FP_COMP_OPS_EXE.SSE2_INTEGER SSE2 integer Uops
    FP_COMP_OPS_EXE.X87 Computational floating-point operations executed
    FP_MMX_TRANS.ANY All Floating Point to and from MMX transitions
    FP_MMX_TRANS.TO_FP Transitions from MMX to Floating Point instructions
    FP_MMX_TRANS.TO_MMX Transitions from Floating Point to MMX instructions
    ILD_STALL.ANY Any Instruction Length Decoder stall cycles
    ILD_STALL.IQ_FULL Instruction Queue full stall cycles
    ILD_STALL.LCP Length Change Prefix stall cycles
    ILD_STALL.MRU Stall cycles due to BPU MRU bypass
    ILD_STALL.REGEN Regen stall cycles
    INST_DECODED.DEC0 Instructions that must be decoded by decoder 0
    INST_QUEUE_WRITE_CYCLES Cycles instructions are written to the instruction queue
    INST_QUEUE_WRITES Instructions written to instruction queue.
    INST_RETIRED.ANY Instructions retired (fixed counter)
    INST_RETIRED.ANY_P Instructions retired (Programmable counter and Precise Event)
    INST_RETIRED.MMX Retired MMX instructions (Precise Event)
    INST_RETIRED.TOTAL_CYCLES Total cycles (Precise Event)
    INST_RETIRED.X87 Retired floating-point operations (Precise Event)
    IO_TRANSACTIONS I/O transactions
    ITLB_FLUSH ITLB flushes
    ITLB_MISS_RETIRED Retired instructions that missed the ITLB (Precise Event)
    ITLB_MISSES.ANY ITLB miss
    ITLB_MISSES.LARGE_WALK_COMPLETED ITLB miss large page walks
    ITLB_MISSES.WALK_COMPLETED ITLB miss page walks
    ITLB_MISSES.WALK_CYCLES ITLB miss page walk cycles
    L1D.M_EVICT L1D cache lines replaced in M state
    L1D.M_REPL L1D cache lines allocated in the M state
    L1D.M_SNOOP_EVICT L1D snoop eviction of cache lines in M state
    L1D.REPL L1 data cache lines allocated
    L1D_CACHE_PREFETCH_LOCK_FB_HIT L1D prefetch load lock accepted in fill buffer
    L1D_PREFETCH.MISS L1D hardware prefetch misses
    L1D_PREFETCH.REQUESTS L1D hardware prefetch requests
    L1D_PREFETCH.TRIGGERS L1D hardware prefetch requests triggered
    L1D_WB_L2.E_STATE L1 writebacks to L2 in E state
    L1D_WB_L2.I_STATE L1 writebacks to L2 in I state (misses)
    L1D_WB_L2.M_STATE L1 writebacks to L2 in M state
    L1D_WB_L2.MESI All L1 writebacks to L2
    L1D_WB_L2.S_STATE L1 writebacks to L2 in S state
    L1I.CYCLES_STALLED L1I instruction fetch stall cycles
    L1I.HITS L1I instruction fetch hits
    L1I.MISSES L1I instruction fetch misses
    L1I.READS L1I Instruction fetches
    L2_DATA_RQSTS.ANY All L2 data requests
    L2_DATA_RQSTS.DEMAND.E_STATE L2 data demand loads in E state
    L2_DATA_RQSTS.DEMAND.I_STATE L2 data demand loads in I state (misses)
    L2_DATA_RQSTS.DEMAND.M_STATE L2 data demand loads in M state
    L2_DATA_RQSTS.DEMAND.MESI L2 data demand requests
    L2_DATA_RQSTS.DEMAND.S_STATE L2 data demand loads in S state
    L2_DATA_RQSTS.PREFETCH.E_STATE L2 data prefetches in E state
    L2_DATA_RQSTS.PREFETCH.I_STATE L2 data prefetches in the I state (misses)
    L2_DATA_RQSTS.PREFETCH.M_STATE L2 data prefetches in M state
    L2_DATA_RQSTS.PREFETCH.MESI All L2 data prefetches
    L2_DATA_RQSTS.PREFETCH.S_STATE L2 data prefetches in the S state
    L2_LINES_IN.ANY L2 lines allocated
    L2_LINES_IN.E_STATE L2 lines allocated in the E state
    L2_LINES_IN.S_STATE L2 lines allocated in the S state
    L2_LINES_OUT.ANY L2 lines evicted
    L2_LINES_OUT.DEMAND_CLEAN L2 lines evicted by a demand request
    L2_LINES_OUT.DEMAND_DIRTY L2 modified lines evicted by a demand request
    L2_LINES_OUT.PREFETCH_CLEAN L2 lines evicted by a prefetch request
    L2_LINES_OUT.PREFETCH_DIRTY L2 modified lines evicted by a prefetch request
    L2_RQSTS.IFETCH_HIT L2 instruction fetch hits
    L2_RQSTS.IFETCH_MISS L2 instruction fetch misses
    L2_RQSTS.IFETCHES L2 instruction fetches
    L2_RQSTS.LD_HIT L2 load hits
    L2_RQSTS.LD_MISS L2 load misses
    L2_RQSTS.LOADS L2 requests
    L2_RQSTS.MISS All L2 misses
    L2_RQSTS.PREFETCH_HIT L2 prefetch hits
    L2_RQSTS.PREFETCH_MISS L2 prefetch misses
    L2_RQSTS.PREFETCHES All L2 prefetches
    L2_RQSTS.REFERENCES All L2 requests
    L2_RQSTS.RFO_HIT L2 RFO hits
    L2_RQSTS.RFO_MISS L2 RFO misses
    L2_RQSTS.RFOS L2 RFO requests
    L2_TRANSACTIONS.ANY All L2 transactions
    L2_TRANSACTIONS.FILL L2 fill transactions
    L2_TRANSACTIONS.IFETCH L2 instruction fetch transactions
    L2_TRANSACTIONS.L1D_WB L1D writeback to L2 transactions
    L2_TRANSACTIONS.LOAD L2 Load transactions
    L2_TRANSACTIONS.PREFETCH L2 prefetch transactions
    L2_TRANSACTIONS.RFO L2 RFO transactions
    L2_TRANSACTIONS.WB L2 writeback to LLC transactions
    L2_WRITE.LOCK.E_STATE L2 demand lock RFOs in E state
    L2_WRITE.LOCK.HIT All demand L2 lock RFOs that hit the cache
    L2_WRITE.LOCK.I_STATE L2 demand lock RFOs in I state (misses)
    L2_WRITE.LOCK.M_STATE L2 demand lock RFOs in M state
    L2_WRITE.LOCK.MESI All demand L2 lock RFOs
    L2_WRITE.LOCK.S_STATE L2 demand lock RFOs in S state
    L2_WRITE.RFO.HIT All L2 demand store RFOs that hit the cache
    L2_WRITE.RFO.I_STATE L2 demand store RFOs in I state (misses)
    L2_WRITE.RFO.M_STATE L2 demand store RFOs in M state
    L2_WRITE.RFO.MESI All L2 demand store RFOs
    L2_WRITE.RFO.S_STATE L2 demand store RFOs in S state
    LARGE_ITLB.HIT Large ITLB hit
    LOAD_BLOCK.OVERLAP_STORE Loads that partially overlap an earlier store
    LOAD_DISPATCH.ANY All loads dispatched
    LOAD_DISPATCH.MOB Loads dispatched from the MOB
    LOAD_DISPATCH.RS Loads dispatched that bypass the MOB
    LOAD_DISPATCH.RS_DELAYED Loads dispatched from stage 305
    LOAD_HIT_PRE Load operations conflicting with software prefetches
    LONGEST_LAT_CACHE.MISS Longest latency cache miss
    LONGEST_LAT_CACHE.REFERENCE Longest latency cache reference
    LSD.ACTIVE Cycles when uops were delivered by the LSD
    LSD.INACTIVE Cycles no uops were delivered by the LSD
    LSD_OVERFLOW Loops that can't stream from the instruction queue
    MACHINE_CLEARS.CYCLES Cycles machine clear asserted
    MACHINE_CLEARS.MEM_ORDER Execution pipeline restart due to Memory ordering conflicts
    MACHINE_CLEARS.SMC Self-Modifying Code detected
    MACRO_INSTS.DECODED Instructions decoded
    MACRO_INSTS.FUSIONS_DECODED Macro-fused instructions decoded
    MEM_INST_RETIRED.LOADS Instructions retired which contains a load (Precise Event)
    MEM_INST_RETIRED.STORES Instructions retired which contains a store (Precise Event)
    MEM_LOAD_RETIRED.DTLB_MISS Retired loads that miss the DTLB (Precise Event)
    MEM_LOAD_RETIRED.HIT_LFB Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
    MEM_LOAD_RETIRED.L1D_HIT Retired loads that hit the L1 data cache (Precise Event)
    MEM_LOAD_RETIRED.L2_HIT Retired loads that hit the L2 cache (Precise Event)
    MEM_LOAD_RETIRED.LLC_MISS Retired loads that miss the LLC cache (Precise Event)
    MEM_LOAD_RETIRED.LLC_UNSHARED_HIT Retired loads that hit valid versions in the LLC cache (Precise Event)
    MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
    MEM_STORE_RETIRED.DTLB_MISS Retired stores that miss the DTLB (Precise Event)
    MISALIGN_MEM_REF.STORE Misaligned store references
    OFFCORE_REQUESTS.ANY All offcore requests
    OFFCORE_REQUESTS.ANY.READ Offcore read requests
    OFFCORE_REQUESTS.ANY.RFO Offcore RFO requests
    OFFCORE_REQUESTS.DEMAND.READ_CODE Offcore demand code read requests
    OFFCORE_REQUESTS.DEMAND.READ_DATA Offcore demand data read requests
    OFFCORE_REQUESTS.DEMAND.RFO Offcore demand RFO requests
    OFFCORE_REQUESTS.L1D_WRITEBACK Offcore L1 data cache writebacks
    OFFCORE_REQUESTS_OUTSTANDING.ANY.READ Outstanding offcore reads
    OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY Cycles offcore reads busy
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE Outstanding offcore demand code reads
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY Cycles offcore demand code read busy
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA Outstanding offcore demand data reads
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY Cycles offcore demand data read busy
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO Outstanding offcore demand RFOs
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY Cycles offcore demand RFOs busy
    OFFCORE_REQUESTS_SQ_FULL Offcore requests blocked due to Super Queue full
    PARTIAL_ADDRESS_ALIAS False dependencies due to partial address aliasing
    RAT_STALLS.ANY All RAT stall cycles
    RAT_STALLS.FLAGS Flag stall cycles
    RAT_STALLS.REGISTERS Partial register stall cycles
    RAT_STALLS.ROB_READ_PORT ROB read port stalls cycles
    RAT_STALLS.SCOREBOARD Scoreboard stall cycles
    RESOURCE_STALLS.ANY Resource related stall cycles
    RESOURCE_STALLS.FPCW FPU control word write stall cycles
    RESOURCE_STALLS.LOAD Load buffer stall cycles
    RESOURCE_STALLS.MXCSR MXCSR rename stall cycles
    RESOURCE_STALLS.OTHER Other Resource related stall cycles
    RESOURCE_STALLS.ROB_FULL ROB full stall cycles
    RESOURCE_STALLS.RS_FULL Reservation Station full stall cycles
    RESOURCE_STALLS.STORE Store buffer stall cycles
    SB_DRAIN.ANY All Store buffer stall cycles
    SEG_RENAME_STALLS Segment rename stall cycles
    SIMD_INT_128.PACK 128 bit SIMD integer pack operations
    SIMD_INT_128.PACKED_ARITH 128 bit SIMD integer arithmetic operations
    SIMD_INT_128.PACKED_LOGICAL 128 bit SIMD integer logical operations
    SIMD_INT_128.PACKED_MPY 128 bit SIMD integer multiply operations
    SIMD_INT_128.PACKED_SHIFT 128 bit SIMD integer shift operations
    SIMD_INT_128.SHUFFLE_MOVE 128 bit SIMD integer shuffle/move operations
    SIMD_INT_128.UNPACK 128 bit SIMD integer unpack operations
    SIMD_INT_64.PACK SIMD integer 64 bit pack operations
    SIMD_INT_64.PACKED_ARITH SIMD integer 64 bit arithmetic operations
    SIMD_INT_64.PACKED_LOGICAL SIMD integer 64 bit logical operations
    SIMD_INT_64.PACKED_MPY SIMD integer 64 bit packed multiply operations
    SIMD_INT_64.PACKED_SHIFT SIMD integer 64 bit shift operations
    SIMD_INT_64.SHUFFLE_MOVE SIMD integer 64 bit shuffle/move operations
    SIMD_INT_64.UNPACK SIMD integer 64 bit unpack operations
    SNOOP_RESPONSE.HIT Thread responded HIT to snoop
    SNOOP_RESPONSE.HITE Thread responded HITE to snoop
    SNOOP_RESPONSE.HITM Thread responded HITM to snoop
    SNOOPQ_REQUESTS.CODE Snoop code requests
    SNOOPQ_REQUESTS.DATA Snoop data requests
    SNOOPQ_REQUESTS.INVALIDATE Snoop invalidate requests
    SNOOPQ_REQUESTS_OUTSTANDING.CODE Outstanding snoop code requests
    SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY Cycles snoop code requests queued
    SNOOPQ_REQUESTS_OUTSTANDING.DATA Outstanding snoop data requests
    SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY Cycles snoop data requests queued
    SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE Outstanding snoop invalidate requests
    SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY Cycles snoop invalidate requests queued
    SQ_FULL_STALL_CYCLES Super Queue full stall cycles
    SQ_MISC.LRU_HINTS Super Queue LRU hints sent to LLC
    SQ_MISC.SPLIT_LOCK Super Queue lock splits across a cache line
    SSEX_UOPS_RETIRED.PACKED_DOUBLE SIMD Packed-Double Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.PACKED_SINGLE SIMD Packed-Single Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.SCALAR_DOUBLE SIMD Scalar-Double Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.SCALAR_SINGLE SIMD Scalar-Single Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.VECTOR_INTEGER SIMD Vector Integer Uops retired (Precise Event)
    STORE_BLOCKS.AT_RET Loads delayed with at-Retirement block code
    STORE_BLOCKS.L1D_BLOCK Cacheable loads delayed with L1D block code
    TWO_UOP_INSTS_DECODED Two Uop instructions decoded
    UOP_UNFUSION Uop unfusions due to FP exceptions
    UOPS_DECODED.ESP_FOLDING Stack pointer instructions decoded
    UOPS_DECODED.ESP_SYNC Stack pointer sync operations
    UOPS_DECODED.MS_CYCLES_ACTIVE Uops decoded by Microcode Sequencer
    UOPS_DECODED.STALL_CYCLES Cycles no Uops are decoded
    UOPS_EXECUTED.CORE_ACTIVE_CYCLES Cycles Uops executed on any port (core count)
    UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 Cycles Uops executed on ports 0-4 (core count)
    UOPS_EXECUTED.CORE_STALL_COUNT Uops executed on any port (core count)
    UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5 Uops executed on ports 0-4 (core count)
    UOPS_EXECUTED.CORE_STALL_CYCLES Cycles no Uops issued on any port (core count)
    UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5 Cycles no Uops issued on ports 0-4 (core count)
    UOPS_EXECUTED.PORT0 Uops executed on port 0
    UOPS_EXECUTED.PORT015 Uops issued on ports 0, 1 or 5
    UOPS_EXECUTED.PORT015_STALL_CYCLES Cycles no Uops issued on ports 0, 1 or 5
    UOPS_EXECUTED.PORT1 Uops executed on port 1
    UOPS_EXECUTED.PORT2_CORE Uops executed on port 2 (core count)
    UOPS_EXECUTED.PORT234_CORE Uops issued on ports 2, 3 or 4
    UOPS_EXECUTED.PORT3_CORE Uops executed on port 3 (core count)
    UOPS_EXECUTED.PORT4_CORE Uops executed on port 4 (core count)
    UOPS_EXECUTED.PORT5 Uops executed on port 5
    UOPS_ISSUED.ANY Uops issued
    UOPS_ISSUED.CORE_STALL_CYCLES Cycles no Uops were issued on any thread
    UOPS_ISSUED.CYCLES_ALL_THREADS Cycles Uops were issued on either thread
    UOPS_ISSUED.FUSED Fused Uops issued
    UOPS_ISSUED.STALL_CYCLES Cycles no Uops were issued
    UOPS_RETIRED.ACTIVE_CYCLES Cycles Uops are being retired
    UOPS_RETIRED.ANY Uops retired (Precise Event)
    UOPS_RETIRED.MACRO_FUSED Macro-fused Uops retired (Precise Event)
    UOPS_RETIRED.RETIRE_SLOTS Retirement slots used (Precise Event)
    UOPS_RETIRED.STALL_CYCLES Cycles Uops are not retiring (Precise Event)
    UOPS_RETIRED.TOTAL_CYCLES Total cycles using precise uop retired event (Precise Event)
    BR_INST_RETIRED.ALL_BRANCHES_PS Retired branch instructions (Precise Event)
    BR_INST_RETIRED.CONDITIONAL_PS Retired conditional branch instructions (Precise Event)
    BR_INST_RETIRED.NEAR_CALL_PS Retired near call instructions (Precise Event)
    BR_INST_RETIRED.NEAR_CALL_R3_PS Retired near call instructions Ring 3 only(Precise Event)
    BR_MISP_RETIRED.ALL_BRANCHES_PS Mispredicted retired branch instructions (Precise Event)
    BR_MISP_RETIRED.CONDITIONAL_PS Mispredicted conditional retired branches (Precise Event)
    BR_MISP_RETIRED.NEAR_CALL_PS Mispredicted near retired calls (Precise Event)
    FP_ASSIST.ALL_PS X87 Floating point assists (Precise Event)
    FP_ASSIST.INPUT_PS X87 Floating poiint assists for invalid input value (Precise Event)
    FP_ASSIST.OUTPUT_PS X87 Floating point assists for invalid output value (Precise Event)
    INST_RETIRED.ANY_P_PS Instructions retired (Programmable counter and Precise Event)
    INST_RETIRED.MMX_PS Retired MMX instructions (Precise Event)
    INST_RETIRED.TOTAL_CYCLES_PS Total cycles (Precise Event)
    INST_RETIRED.X87_PS Retired floating-point operations (Precise Event)
    ITLB_MISS_RETIRED_PS Retired instructions that missed the ITLB (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0 Memory instructions retired above 0 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024 Memory instructions retired above 1024 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128 Memory instructions retired above 128 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16 Memory instructions retired above 16 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384 Memory instructions retired above 16384 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048 Memory instructions retired above 2048 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256 Memory instructions retired above 256 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32 Memory instructions retired above 32 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768 Memory instructions retired above 32768 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4 Memory instructions retired above 4 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096 Memory instructions retired above 4096 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512 Memory instructions retired above 512 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64 Memory instructions retired above 64 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8 Memory instructions retired above 8 clocks (Precise Event)
    MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192 Memory instructions retired above 8192 clocks (Precise Event)
    MEM_INST_RETIRED.LOADS_PS Instructions retired which contains a load (Precise Event)
    MEM_INST_RETIRED.STORES_PS Instructions retired which contains a store (Precise Event)
    MEM_LOAD_RETIRED.DTLB_MISS_PS Retired loads that miss the DTLB (Precise Event)
    MEM_LOAD_RETIRED.HIT_LFB_PS Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
    MEM_LOAD_RETIRED.L1D_HIT_PS Retired loads that hit the L1 data cache (Precise Event)
    MEM_LOAD_RETIRED.L2_HIT_PS Retired loads that hit the L2 cache (Precise Event)
    MEM_LOAD_RETIRED.LLC_MISS_PS Retired loads that miss the LLC cache (Precise Event)
    MEM_LOAD_RETIRED.LLC_UNSHARED_HIT_PS Retired loads that hit valid versions in the LLC cache (Precise Event)
    MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM_PS Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
    MEM_STORE_RETIRED.DTLB_MISS_PS Retired stores that miss the DTLB (Precise Event)
    SSEX_UOPS_RETIRED.PACKED_DOUBLE_PS SIMD Packed-Double Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.PACKED_SINGLE_PS SIMD Packed-Single Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.SCALAR_DOUBLE_PS SIMD Scalar-Double Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.SCALAR_SINGLE_PS SIMD Scalar-Single Uops retired (Precise Event)
    SSEX_UOPS_RETIRED.VECTOR_INTEGER_PS SIMD Vector Integer Uops retired (Precise Event)
    UOPS_RETIRED.ACTIVE_CYCLES_PS Cycles Uops are being retired
    UOPS_RETIRED.ANY_PS Uops retired (Precise Event)
    UOPS_RETIRED.MACRO_FUSED_PS Macro-fused Uops retired (Precise Event)
    UOPS_RETIRED.RETIRE_SLOTS_PS Retirement slots used (Precise Event)
    UOPS_RETIRED.STALL_CYCLES_PS Cycles Uops are not retiring (Precise Event)
    UOPS_RETIRED.TOTAL_CYCLES_PS Total cycles using precise uop retired event (Precise Event)
    UNC_ADDR_OPCODE_MATCH.IOH.NONE TBD
    UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDI TBD
    UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDS TBD
    UNC_ADDR_OPCODE_MATCH.IOH.RSPIWB TBD
    UNC_ADDR_OPCODE_MATCH.LOCAL.NONE TBD
    UNC_ADDR_OPCODE_MATCH.LOCAL.RSPFWDI hitm in local LLC rfo snoop
    UNC_ADDR_OPCODE_MATCH.LOCAL.RSPFWDS local LLC in F or S, load snoop
    UNC_ADDR_OPCODE_MATCH.LOCAL.RSPIWB hitm in local LLC, load snoop
    UNC_ADDR_OPCODE_MATCH.REMOTE.NONE TBD
    UNC_ADDR_OPCODE_MATCH.REMOTE.RSPFWDI hitm in remote LLC, rfo
    UNC_ADDR_OPCODE_MATCH.REMOTE.RSPFWDS remote LLC in F or S, load
    UNC_ADDR_OPCODE_MATCH.REMOTE.RSPIWB hitm in remote LLC, load
    UNC_CLOCKTICKS Uncore clockticks
    UNC_CYCLES_UNHALTED_LLC_FULL_DISABLE Cycles LLC disabled
    UNC_CYCLES_UNHALTED_LLC_FULL_ENABLE Cycles package not halted
    UNC_DRAM_OPEN.CH0 DRAM Channel 0 open commands
    UNC_DRAM_OPEN.CH1 DRAM Channel 1 open commands
    UNC_DRAM_OPEN.CH2 DRAM Channel 2 open commands
    UNC_DRAM_PAGE_CLOSE.CH0 DRAM Channel 0 page close
    UNC_DRAM_PAGE_CLOSE.CH1 DRAM Channel 1 page close
    UNC_DRAM_PAGE_CLOSE.CH2 DRAM Channel 2 page close
    UNC_DRAM_PAGE_MISS.CH0 DRAM Channel 0 page miss
    UNC_DRAM_PAGE_MISS.CH1 DRAM Channel 1 page miss
    UNC_DRAM_PAGE_MISS.CH2 DRAM Channel 2 page miss
    UNC_DRAM_PRE_ALL.CH0 DRAM Channel 0 precharge all commands
    UNC_DRAM_PRE_ALL.CH1 DRAM Channel 1 precharge all commands
    UNC_DRAM_PRE_ALL.CH2 DRAM Channel 2 precharge all commands
    UNC_DRAM_READ_CAS.AUTOPRE_CH0 DRAM Channel 0 read CAS auto page close commands
    UNC_DRAM_READ_CAS.AUTOPRE_CH1 DRAM Channel 1 read CAS auto page close commands
    UNC_DRAM_READ_CAS.AUTOPRE_CH2 DRAM Channel 2 read CAS auto page close commands
    UNC_DRAM_READ_CAS.CH0 DRAM Channel 0 read CAS commands
    UNC_DRAM_READ_CAS.CH1 DRAM Channel 1 read CAS commands
    UNC_DRAM_READ_CAS.CH2 DRAM Channel 2 read CAS commands
    UNC_DRAM_REFRESH.CH0 DRAM Channel 0 refresh commands
    UNC_DRAM_REFRESH.CH1 DRAM Channel 1 refresh commands
    UNC_DRAM_REFRESH.CH2 DRAM Channel 2 refresh commands
    UNC_DRAM_THERMAL_THROTTLED Cycles DRAM thermal throttled
    UNC_DRAM_WRITE_CAS.AUTOPRE_CH0 DRAM Channel 0 write CAS auto page close commands
    UNC_DRAM_WRITE_CAS.AUTOPRE_CH1 DRAM Channel 1 write CAS auto page close commands
    UNC_DRAM_WRITE_CAS.AUTOPRE_CH2 DRAM Channel 2 write CAS auto page close commands
    UNC_DRAM_WRITE_CAS.CH0 DRAM Channel 0 write CAS commands
    UNC_DRAM_WRITE_CAS.CH1 DRAM Channel 1 write CAS commands
    UNC_DRAM_WRITE_CAS.CH2 DRAM Channel 2 write CAS commands
    UNC_GQ_ALLOC.PEER_PROBE_TRACKER GQ peer probe tracker requests
    UNC_GQ_ALLOC.READ_TRACKER GQ read tracker requests
    UNC_GQ_ALLOC.RT_LLC_MISS GQ read tracker LLC misses
    UNC_GQ_ALLOC.RT_TO_LLC_RESP GQ read tracker LLC requests
    UNC_GQ_ALLOC.RT_TO_RTID_ACQUIRED GQ read tracker LLC miss to RTID acquired
    UNC_GQ_ALLOC.WRITE_TRACKER GQ write tracker LLC misses
    UNC_GQ_ALLOC.WT_TO_RTID_ACQUIRED GQ write tracker LLC miss to RTID acquired
    UNC_GQ_CYCLES_FULL.PEER_PROBE_TRACKER Cycles GQ peer probe tracker is full.
    UNC_GQ_CYCLES_FULL.READ_TRACKER Cycles GQ read tracker is full.
    UNC_GQ_CYCLES_FULL.WRITE_TRACKER Cycles GQ write tracker is full.
    UNC_GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER Cycles GQ peer probe tracker is busy
    UNC_GQ_CYCLES_NOT_EMPTY.READ_TRACKER Cycles GQ read tracker is busy
    UNC_GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER Cycles GQ write tracker is busy
    UNC_GQ_DATA.FROM_CORES_02 Cycles GQ data is imported from Cores 0 and 2
    UNC_GQ_DATA.FROM_CORES_13 Cycles GQ data is imported from Cores 1 and 3
    UNC_GQ_DATA.FROM_IMC Cycles GQ data is imported from Integrated Memory Controller
    UNC_GQ_DATA.FROM_LLC Cycles GQ data is imported from LLC
    UNC_GQ_DATA.FROM_QPI Cycles GQ data is imported from Quickpath interface
    UNC_GQ_DATA.TO_CORES Cycles GQ data sent to cores
    UNC_GQ_DATA.TO_LLC Cycles GQ data sent to LLC
    UNC_GQ_DATA.TO_QPI_IMC Cycles GQ data sent to the interconnect or IMC
    UNC_GQ_OCCUPANCY.PEER_PROBE_TRACKER GQ peer probe tracker LLC miss occupancy
    UNC_GQ_OCCUPANCY.READ_TRACKER GQ read tracker occupancy
    UNC_GQ_OCCUPANCY.RT_LLC_MISS GQ read tracker LLC miss occupancy
    UNC_GQ_OCCUPANCY.RT_LLC_MISS_NOT_EMPTY Cycles GQ read tracker LLC miss queued
    UNC_GQ_OCCUPANCY.RT_TO_LLC_RESP GQ read tracker LLC hit occupancy
    UNC_GQ_OCCUPANCY.RT_TO_LLC_RESP_NOT_EMPTY GQ read tracker LLC request queued
    UNC_GQ_OCCUPANCY.RT_TO_RTID_ACQUIRED GQ read tracker LLC miss to RTID acquired occupancy
    UNC_GQ_OCCUPANCY.WRITE_TRACKER GQ write tracker LLC miss occupancy
    UNC_GQ_OCCUPANCY.WT_TO_RTID_ACQUIRED GQ write tracker LLC miss to RTID acquired occupancy
    UNC_GQ_SNOOP.GOTO_I Remote snoop requests to change cache line to I state
    UNC_GQ_SNOOP.GOTO_I_HIT_E Remote snoop requests to change cache line from E to I state
    UNC_GQ_SNOOP.GOTO_I_HIT_F Remote snoop requests to change cache line from F to I state
    UNC_GQ_SNOOP.GOTO_I_HIT_M Remote snoop requests to change cache line from M to I state
    UNC_GQ_SNOOP.GOTO_I_HIT_S Remote snoop requests to change cache line from S to I state
    UNC_GQ_SNOOP.GOTO_S Remote snoop requests to change cache line to S state
    UNC_GQ_SNOOP.GOTO_S_HIT_E Remote snoop requests to change cache line from E to S state
    UNC_GQ_SNOOP.GOTO_S_HIT_F Remote snoop requests to change cache line from F to S state
    UNC_GQ_SNOOP.GOTO_S_HIT_M Remote snoop requests to change cache line from M to S state
    UNC_GQ_SNOOP.GOTO_S_HIT_S Remote snoop requests to change cache line from S to S state
    UNC_IMC_BUSY.READ.CH0 Cycles IMC channel 0 busy with a read request
    UNC_IMC_BUSY.READ.CH1 Cycles IMC channel 1 busy with a read request
    UNC_IMC_BUSY.READ.CH2 Cycles IMC channel 2 busy with a read request
    UNC_IMC_BUSY.WRITE.CH0 Cycles IMC channel 0 busy with a write request
    UNC_IMC_BUSY.WRITE.CH1 Cycles IMC channel 1 busy with a write request
    UNC_IMC_BUSY.WRITE.CH2 Cycles IMC channel 2 busy with a write request
    UNC_IMC_CANCEL.ANY IMC cancels
    UNC_IMC_CANCEL.CH0 IMC channel 0 cancels
    UNC_IMC_CANCEL.CH1 IMC channel 1 cancels
    UNC_IMC_CANCEL.CH2 IMC channel 2 cancels
    UNC_IMC_CRITICAL_PRIORITY_READS.ANY IMC critical priority read requests
    UNC_IMC_CRITICAL_PRIORITY_READS.CH0 IMC channel 0 critical priority read requests
    UNC_IMC_CRITICAL_PRIORITY_READS.CH1 IMC channel 1 critical priority read requests
    UNC_IMC_CRITICAL_PRIORITY_READS.CH2 IMC channel 2 critical priority read requests
    UNC_IMC_HIGH_PRIORITY_READS.ANY IMC high priority read requests
    UNC_IMC_HIGH_PRIORITY_READS.CH0 IMC channel 0 high priority read requests
    UNC_IMC_HIGH_PRIORITY_READS.CH1 IMC channel 1 high priority read requests
    UNC_IMC_HIGH_PRIORITY_READS.CH2 IMC channel 2 high priority read requests
    UNC_IMC_ISOC_FULL.READ.CH0 Cycles DRAM channel 0 full with ISOC read requests
    UNC_IMC_ISOC_FULL.READ.CH1 Cycles DRAM channel 1 full with ISOC read requests
    UNC_IMC_ISOC_FULL.READ.CH2 Cycles DRAM channel 2 full with ISOC read requests
    UNC_IMC_ISOC_FULL.WRITE.CH0 Cycles DRAM channel 0 full with ISOC write requests
    UNC_IMC_ISOC_FULL.WRITE.CH1 Cycles DRAM channel 1 full with ISOC write requests
    UNC_IMC_ISOC_FULL.WRITE.CH2 Cycles DRAM channel 2 full with ISOC write requests
    UNC_IMC_ISOC_OCCUPANCY.ANY IMC ISOC read request occupancy
    UNC_IMC_ISOC_OCCUPANCY.CH0 IMC channel 0 ISOC read request occupancy
    UNC_IMC_ISOC_OCCUPANCY.CH1 IMC channel 1 ISOC read request occupancy
    UNC_IMC_ISOC_OCCUPANCY.CH2 IMC channel 2 ISOC read request occupancy
    UNC_IMC_NORMAL_OCCUPANCY.ANY IMC normal read request occupancy
    UNC_IMC_NORMAL_OCCUPANCY.CH0 IMC channel 0 normal read request occupancy
    UNC_IMC_NORMAL_OCCUPANCY.CH1 IMC channel 1 normal read request occupancy
    UNC_IMC_NORMAL_OCCUPANCY.CH2 IMC channel 2 normal read request occupancy
    UNC_IMC_NORMAL_READS.ANY IMC normal read requests
    UNC_IMC_NORMAL_READS.CH0 IMC channel 0 normal read requests
    UNC_IMC_NORMAL_READS.CH1 IMC channel 1 normal read requests
    UNC_IMC_NORMAL_READS.CH2 IMC channel 2 normal read requests
    UNC_IMC_PRIORITY_UPDATES.ANY IMC priority updates
    UNC_IMC_PRIORITY_UPDATES.CH0 IMC channel 0 priority updates
    UNC_IMC_PRIORITY_UPDATES.CH1 IMC channel 1 priority updates
    UNC_IMC_PRIORITY_UPDATES.CH2 IMC channel 2 priority updates
    UNC_IMC_RETRY.ANY IMC retries
    UNC_IMC_RETRY.CH0 IMC Channel 0 retries
    UNC_IMC_RETRY.CH1 IMC Channel 1 retries
    UNC_IMC_RETRY.CH2 IMC Channel 2 retries
    UNC_IMC_WRITES.FULL.ANY IMC full cache line writes
    UNC_IMC_WRITES.FULL.CH0 IMC channel 0 full cache line writes
    UNC_IMC_WRITES.FULL.CH1 IMC channel 1 full cache line writes
    UNC_IMC_WRITES.FULL.CH2 IMC channel 2 full cache line writes
    UNC_IMC_WRITES.PARTIAL.ANY IMC partial cache line writes
    UNC_IMC_WRITES.PARTIAL.CH0 IMC channel 0 partial cache line writes
    UNC_IMC_WRITES.PARTIAL.CH1 IMC channel 1 partial cache line writes
    UNC_IMC_WRITES.PARTIAL.CH2 IMC channel 2 partial cache line writes
    UNC_LLC_HITS.ANY Number of LLC hits
    UNC_LLC_HITS.PROBE Number of LLC peer probe hits
    UNC_LLC_HITS.READ Number of LLC read hits
    UNC_LLC_HITS.WRITEBACKS Number of LLC write hits
    UNC_LLC_LINES_IN.ANY LLC lines allocated
    UNC_LLC_LINES_IN.E_STATE LLC lines allocated in E state
    UNC_LLC_LINES_IN.F_STATE LLC lines allocated in F state
    UNC_LLC_LINES_IN.M_STATE LLC lines allocated in M state
    UNC_LLC_LINES_IN.S_STATE LLC lines allocated in S state
    UNC_LLC_LINES_OUT.ANY LLC lines victimized
    UNC_LLC_LINES_OUT.E_STATE LLC lines victimized in E state
    UNC_LLC_LINES_OUT.F_STATE LLC lines victimized in F state
    UNC_LLC_LINES_OUT.I_STATE LLC lines victimized in I state
    UNC_LLC_LINES_OUT.M_STATE LLC lines victimized in M state
    UNC_LLC_LINES_OUT.S_STATE LLC lines victimized in S state
    UNC_LLC_MISS.ANY Number of LLC misses
    UNC_LLC_MISS.PROBE Number of LLC peer probe misses
    UNC_LLC_MISS.READ Number of LLC read misses
    UNC_LLC_MISS.WRITEBACKS Number of LLC write misses
    UNC_PROCHOT_ASSERTION PROCHOT system assertions
    UNC_QHL_ADDRESS_CONFLICTS.2WAY QHL 2 way address conflicts
    UNC_QHL_ADDRESS_CONFLICTS.3WAY QHL 3 way address conflicts
    UNC_QHL_ADDRESS_CONFLICTS.NONE QHL no address conflicts
    UNC_QHL_CONFLICT_CYCLES.IOH QHL IOH Tracker conflict cycles
    UNC_QHL_CONFLICT_CYCLES.LOCAL QHL Local Tracker conflict cycles
    UNC_QHL_CONFLICT_CYCLES.REMOTE QHL Remote Tracker conflict cycles
    UNC_QHL_CYCLES_FULL.IOH Cycles QHL IOH Tracker is full
    UNC_QHL_CYCLES_FULL.LOCAL Cycles QHL Local Tracker is full
    UNC_QHL_CYCLES_FULL.REMOTE Cycles QHL Remote Tracker is full
    UNC_QHL_CYCLES_NOT_EMPTY.IOH Cycles QHL IOH tracker is busy
    UNC_QHL_CYCLES_NOT_EMPTY.LOCAL Cycles QHL local tracker is busy
    UNC_QHL_CYCLES_NOT_EMPTY.REMOTE Cycles QHL remote tracker is busy
    UNC_QHL_FRC_ACK_CNFLTS.ANY QHL FrcAckCnflts sent
    UNC_QHL_FRC_ACK_CNFLTS.IOH QHL FrcAckCnflts sent to IOH
    UNC_QHL_FRC_ACK_CNFLTS.LOCAL QHL FrcAckCnflts sent to local home
    UNC_QHL_FRC_ACK_CNFLTS.REMOTE QHL FrcAckCnflts sent to remote home
    UNC_QHL_OCCUPANCY.IOH QHL IOH tracker allocate to deallocate occupancy
    UNC_QHL_OCCUPANCY.LOCAL QHL local tracker allocate to deallocate occupancy
    UNC_QHL_OCCUPANCY.REMOTE QHL remote tracker allocate to deallocate occupancy
    UNC_QHL_REQUESTS.IOH_READS Quickpath Home Logic IOH read requests
    UNC_QHL_REQUESTS.IOH_WRITES Quickpath Home Logic IOH write requests
    UNC_QHL_REQUESTS.LOCAL_READS Quickpath Home Logic local read requests
    UNC_QHL_REQUESTS.LOCAL_WRITES Quickpath Home Logic local write requests
    UNC_QHL_REQUESTS.REMOTE_READS Quickpath Home Logic remote read requests
    UNC_QHL_REQUESTS.REMOTE_WRITES Quickpath Home Logic remote write requests
    UNC_QHL_SLEEPS.IOH_CONFLICT Sleeps due to IOH address conflicts
    UNC_QHL_SLEEPS.IOH_ORDER Sleeps due to IOH order conflicts
    UNC_QHL_SLEEPS.LOCAL_CONFLICT Sleeps due to local address conflicts
    UNC_QHL_SLEEPS.LOCAL_ORDER Sleeps due to local order conflicts
    UNC_QHL_SLEEPS.REMOTE_CONFLICT Sleeps due to remote address conflicts
    UNC_QHL_SLEEPS.REMOTE_ORDER Sleeps due to remote order conflicts
    UNC_QHL_TO_IMC_BYPASS Number of requests to IMC that bypass QHL
    UNC_QPI_RESERVED_CYCLES.DRS_NDR.LINK_0 Cycles QPI DRS/NDR Link 0 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.DRS_NDR.LINK_1 Cycles QPI DRS/NDR Link 1 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.HOME.LINK_0 Cycles QPI Home Link 0 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.HOME.LINK_1 Cycles QPI Home Link 1 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.NCS_NCB.LINK_0 Cycles QPI NCS/NCB Link 0 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.NCS_NCB.LINK_1 Cycles QPI NCS/NCB Link 1 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.SNOOP.LINK_0 Cycles QPI Snoop Link 0 reserved for forward progress
    UNC_QPI_RESERVED_CYCLES.SNOOP.LINK_1 Cycles QPI Snoop Link 1 reserved for forward progress
    UNC_SNP_RESP_TO_LOCAL_HOME.CONFLICT Local home conflict snoop response
    UNC_SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE Local home snoop response - LLC has forwarded a modified cache line
    UNC_SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE Local home snoop response - LLC forwarding cache line in S state.
    UNC_SNP_RESP_TO_LOCAL_HOME.HIT Local home snoop response - LLC HIT
    UNC_SNP_RESP_TO_LOCAL_HOME.HITM Local home snoop response - LLC HITM
    UNC_SNP_RESP_TO_LOCAL_HOME.I_STATE Local home snoop response - LLC does not have cache line
    UNC_SNP_RESP_TO_LOCAL_HOME.S_STATE Local home snoop response - LLC has cache line in S state
    UNC_SNP_RESP_TO_LOCAL_HOME.WB Local home snoop response - LLC has cache line in the M state
    UNC_SNP_RESP_TO_REMOTE_HOME.CONFLICT Remote home conflict snoop response
    UNC_SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE Remote home snoop response - LLC has forwarded a modified cache line
    UNC_SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE Remote home snoop response - LLC forwarding cache line in S state.
    UNC_SNP_RESP_TO_REMOTE_HOME.HIT Remote home snoop response - LLC HIT
    UNC_SNP_RESP_TO_REMOTE_HOME.HITM Remote home snoop response - LLC HITM
    UNC_SNP_RESP_TO_REMOTE_HOME.I_STATE Remote home snoop response - LLC does not have cache line
    UNC_SNP_RESP_TO_REMOTE_HOME.S_STATE Remote home snoop response - LLC has cache line in S state
    UNC_SNP_RESP_TO_REMOTE_HOME.WB Remote home snoop response - LLC has cache line in the M state
    UNC_THERMAL_THROTTLED.CORE_0 Cycles core 0 thermal throttled
    UNC_THERMAL_THROTTLED.CORE_1 Cycles core 1 thermal throttled
    UNC_THERMAL_THROTTLED.CORE_2 Cycles core 2 thermal throttled
    UNC_THERMAL_THROTTLED.CORE_3 Cycles core 3 thermal throttled
    UNC_THERMAL_THROTTLING_PROCHOT.CORE_0 Cycles core 0 PROCHOT throttled
    UNC_THERMAL_THROTTLING_PROCHOT.CORE_1 Cycles core 1 PROCHOT throttled
    UNC_THERMAL_THROTTLING_PROCHOT.CORE_2 Cycles core 2 PROCHOT throttled
    UNC_THERMAL_THROTTLING_PROCHOT.CORE_3 Cycles core 3 PROCHOT throttled
    UNC_THERMAL_THROTTLING_TEMP.CORE_0 Cycles core 0 above thermal throttling temperature
    UNC_THERMAL_THROTTLING_TEMP.CORE_1 Cycles core 1 above thermal throttling temperature
    UNC_THERMAL_THROTTLING_TEMP.CORE_2 Cycles core 2 above thermal throttling temperature
    UNC_THERMAL_THROTTLING_TEMP.CORE_3 Cycles core 3 above thermal throttling temperature
    UNC_TURBO_MODE.CORE_0 Cycles core 0 in turbo mode
    UNC_TURBO_MODE.CORE_1 Cycles core 1 in turbo mode
    UNC_TURBO_MODE.CORE_2 Cycles core 2 in turbo mode
    UNC_TURBO_MODE.CORE_3 Cycles core 3 in turbo mode