Intel® Microarchitecture Code Named Ivy Bridge Events

This section provides reference for hardware events that can be monitored for the CPU(s):

  • 3rd generation Intel® Core™ processor family
  • EventName Description
    INST_RETIRED.ANY Instructions retired from execution.
    CPU_CLK_UNHALTED.THREAD Core cycles when the thread is not in halt state.
    CPU_CLK_UNHALTED.REF_TSC Reference cycles when the core is not in halt state.
    LD_BLOCKS.STORE_FORWARD Loads blocked by overlapping with store buffer that cannot be forwarded.
    LD_BLOCKS.NO_SR The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
    MISALIGN_MEM_REF.LOADS Speculative cache-line split load uops dispatched to L1D.
    MISALIGN_MEM_REF.STORES Speculative cache-line split Store-address uops dispatched to L1D.
    LD_BLOCKS_PARTIAL.ADDRESS_ALIAS False dependencies in MOB due to partial compare on address.
    DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED Page walk for a large page completed for Demand load.
    INT_MISC.RECOVERY_CYCLES Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)
    INT_MISC.RECOVERY_STALLS_COUNT Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)
    UOPS_ISSUED.ANY Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
    UOPS_ISSUED.STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.
    UOPS_ISSUED.CORE_STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.
    UOPS_ISSUED.FLAGS_MERGE Number of flags-merge uops allocated. Such uops adds delay.
    UOPS_ISSUED.SLOW_LEA Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
    UOPS_ISSUED.SINGLE_MUL Number of multiply packed/scalar single precision uops allocated.
    FP_COMP_OPS_EXE.X87 Counts number of X87 uops executed.
    FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_PACKED_SINGLE Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE Counts number of SSE* or AVX-128 double precision FP scalar uops executed.
    SIMD_FP_256.PACKED_SINGLE Counts 256-bit packed single-precision floating-point instructions.
    SIMD_FP_256.PACKED_DOUBLE Counts 256-bit packed double-precision floating-point instructions.
    ARITH.FPU_DIV_ACTIVE Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.
    ARITH.FPU_DIV Divide operations executed.
    L2_RQSTS.DEMAND_DATA_RD_HIT Demand Data Read requests that hit L2 cache.
    L2_RQSTS.RFO_HIT RFO requests that hit L2 cache.
    L2_RQSTS.RFO_MISS Counts the number of store RFO requests that miss the L2 cache.
    L2_RQSTS.CODE_RD_HIT Number of instruction fetches that hit the L2 cache.
    L2_RQSTS.CODE_RD_MISS Number of instruction fetches that missed the L2 cache.
    L2_RQSTS.PF_HIT Counts all L2 HW prefetcher requests that hit L2.
    L2_RQSTS.PF_MISS Counts all L2 HW prefetcher requests that missed L2.
    L2_RQSTS.ALL_DEMAND_DATA_RD Counts any demand and L1 HW prefetch data load requests to L2.
    L2_RQSTS.ALL_RFO Counts all L2 store RFO requests.
    L2_RQSTS.ALL_CODE_RD Counts all L2 code requests.
    L2_RQSTS.ALL_PF Counts all L2 HW prefetcher requests.
    L2_STORE_LOCK_RQSTS.MISS RFOs that miss cache lines.
    L2_STORE_LOCK_RQSTS.HIT_M RFOs that hit cache lines in M state.
    L2_STORE_LOCK_RQSTS.ALL RFOs that access cache lines in any state.
    L2_L1D_WB_RQSTS.MISS Not rejected writebacks that missed LLC.
    L2_L1D_WB_RQSTS.HIT_E Not rejected writebacks from L1D to L2 cache lines in E state.
    L2_L1D_WB_RQSTS.HIT_M Not rejected writebacks from L1D to L2 cache lines in M state.
    L2_L1D_WB_RQSTS.ALL Not rejected writebacks from L1D to L2 cache lines in any state.
    LONGEST_LAT_CACHE.MISS This event counts each cache miss condition for references to the last level cache.
    LONGEST_LAT_CACHE.REFERENCE This event counts requests originating from the core that reference a cache line in the last level cache.
    CPU_CLK_UNHALTED.THREAD_P Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK Increments at the frequency of XCLK (100 MHz) when not halted.
    CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other is halted.
    L1D_PEND_MISS.PENDING Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.
    L1D_PEND_MISS.PENDING_CYCLES Cycles with L1D load Misses outstanding.
    DTLB_STORE_MISSES.MISS_CAUSES_A_WALK Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).
    DTLB_STORE_MISSES.WALK_COMPLETED Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).
    DTLB_STORE_MISSES.WALK_DURATION Cycles PMH is busy with this walk.
    DTLB_STORE_MISSES.STLB_HIT Store operations that miss the first TLB level but hit the second and do not cause page walks.
    LOAD_HIT_PRE.SW_PF Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
    LOAD_HIT_PRE.HW_PF Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
    EPT.WALK_CYCLES Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
    L1D.REPLACEMENT Counts the number of lines brought into the L1 data cache.
    MOVE_ELIMINATION.INT_NOT_ELIMINATED Number of integer Move Elimination candidate uops that were not eliminated.
    MOVE_ELIMINATION.SIMD_NOT_ELIMINATED Number of SIMD Move Elimination candidate uops that were not eliminated.
    MOVE_ELIMINATION.INT_ELIMINATED Number of integer Move Elimination candidate uops that were eliminated.
    MOVE_ELIMINATION.SIMD_ELIMINATED Number of SIMD Move Elimination candidate uops that were eliminated.
    CPL_CYCLES.RING0 Unhalted core cycles when the thread is in ring 0.
    CPL_CYCLES.RING123 Unhalted core cycles when the thread is not in ring 0.
    CPL_CYCLES.RING0_TRANS Number of intervals between processor halts while thread is in ring 0.
    RS_EVENTS.EMPTY_CYCLES Cycles the RS is empty for the thread.
    DTLB_LOAD_MISSES.STLB_HIT Counts load operations that missed 1st level DTLB but hit the 2nd level.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.
    OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
    LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
    LOCK_CYCLES.CACHE_LOCK_DURATION Cycles in which the L1D is locked.
    IDQ.EMPTY Counts cycles the IDQ is empty.
    IDQ.MITE_UOPS Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.
    IDQ.DSB_UOPS Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.
    IDQ.MS_DSB_UOPS Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
    IDQ.MS_MITE_UOPS Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.
    IDQ.MS_UOPS Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.
    IDQ.MS_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MITE_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.
    IDQ.DSB_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
    IDQ.MS_DSB_CYCLES Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MS_DSB_OCCUR Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.
    IDQ.ALL_DSB_CYCLES_4_UOPS Counts cycles DSB is delivered four uops. Set Cmask = 4.
    IDQ.ALL_DSB_CYCLES_ANY_UOPS Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
    IDQ.ALL_MITE_CYCLES_4_UOPS Counts cycles MITE is delivered four uops. Set Cmask = 4.
    IDQ.ALL_MITE_CYCLES_ANY_UOPS Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
    IDQ.MITE_ALL_UOPS Number of uops delivered to IDQ from any path.
    ICACHE.HIT Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.
    ICACHE.MISSES Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.
    ICACHE.IFETCH_STALL Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.
    ITLB_MISSES.MISS_CAUSES_A_WALK Misses in all ITLB levels that cause page walks.
    ITLB_MISSES.WALK_COMPLETED Misses in all ITLB levels that cause completed page walks.
    ITLB_MISSES.WALK_DURATION Cycle PMH is busy with a walk.
    ITLB_MISSES.STLB_HIT Number of cache load STLB hits. No page walk.
    ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED Completed page walks in ITLB due to STLB load misses for large pages.
    ILD_STALL.LCP Stalls caused by changing prefix length of the instruction.
    ILD_STALL.IQ_FULL Stall cycles due to IQ is full.
    BR_INST_EXEC.NONTAKEN_CONDITIONAL Not taken macro-conditional branches.
    BR_INST_EXEC.TAKEN_CONDITIONAL Taken speculative and retired macro-conditional branches.
    BR_INST_EXEC.TAKEN_DIRECT_JUMP Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.
    BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired indirect branches excluding calls and returns.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN Taken speculative and retired indirect branches with return mnemonic.
    BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL Taken speculative and retired direct near calls.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired indirect calls.
    BR_INST_EXEC.ALL_CONDITIONAL Speculative and retired macro-conditional branches.
    BR_INST_EXEC.ALL_DIRECT_JMP Speculative and retired macro-unconditional branches excluding calls and indirects.
    BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Speculative and retired indirect branches excluding calls and returns.
    BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN Speculative and retired indirect return branches.
    BR_INST_EXEC.ALL_DIRECT_NEAR_CALL Speculative and retired direct near calls.
    BR_INST_EXEC.ALL_BRANCHES Counts all near executed branches (not necessarily retired).
    BR_MISP_EXEC.NONTAKEN_CONDITIONAL Not taken speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.TAKEN_CONDITIONAL Taken speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.TAKEN_RETURN_NEAR Taken speculative and retired mispredicted indirect branches with return mnemonic.
    BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired mispredicted indirect calls.
    BR_MISP_EXEC.ALL_CONDITIONAL Speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.ALL_BRANCHES Counts all near executed branches (not necessarily retired).
    IDQ_UOPS_NOT_DELIVERED.CORE Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE Cycles with less than 2 uops delivered by the front end.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE Cycles with less than 3 uops delivered by the front end.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
    UOPS_DISPATCHED_PORT.PORT_0 Cycles which a Uop is dispatched on port 0.
    UOPS_DISPATCHED_PORT.PORT_1 Cycles which a Uop is dispatched on port 1.
    UOPS_DISPATCHED_PORT.PORT_4 Cycles which a Uop is dispatched on port 4.
    UOPS_DISPATCHED_PORT.PORT_5 Cycles which a Uop is dispatched on port 5.
    UOPS_DISPATCHED_PORT.PORT_0_CORE Cycles per core when uops are dispatched to port 0.
    UOPS_DISPATCHED_PORT.PORT_1_CORE Cycles per core when uops are dispatched to port 1.
    UOPS_DISPATCHED_PORT.PORT_4_CORE Cycles per core when uops are dispatched to port 4.
    UOPS_DISPATCHED_PORT.PORT_5_CORE Cycles per core when uops are dispatched to port 5.
    UOPS_DISPATCHED_PORT.PORT_2 Cycles which a Uop is dispatched on port 2.
    UOPS_DISPATCHED_PORT.PORT_3 Cycles which a Uop is dispatched on port 3.
    UOPS_DISPATCHED_PORT.PORT_2_CORE Uops dispatched to port 2, loads and stores per core (speculative and retired).
    UOPS_DISPATCHED_PORT.PORT_3_CORE Cycles per core when load or STA uops are dispatched to port 3.
    RESOURCE_STALLS.ANY Cycles Allocation is stalled due to Resource Related reason.
    RESOURCE_STALLS.RS Cycles stalled due to no eligible RS entry available.
    RESOURCE_STALLS.SB Cycles stalled due to no store buffers available (not including draining form sync).
    RESOURCE_STALLS.ROB Cycles stalled due to re-order buffer full.
    CYCLE_ACTIVITY.CYCLES_L2_PENDING Cycles with pending L2 miss loads. Set AnyThread to count per core.
    CYCLE_ACTIVITY.CYCLES_L1D_PENDING Cycles with pending L1 cache miss loads. Set AnyThread to count per core.
    CYCLE_ACTIVITY.CYCLES_LDM_PENDING Cycles with pending memory loads. Set AnyThread to count per core.
    CYCLE_ACTIVITY.CYCLES_NO_EXECUTE Total execution stalls.
    CYCLE_ACTIVITY.STALLS_L2_PENDING Number of loads missed L2.
    CYCLE_ACTIVITY.STALLS_LDM_PENDING Execution stalls due to memory subsystem.
    CYCLE_ACTIVITY.STALLS_L1D_PENDING Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.
    LSD.UOPS Number of Uops delivered by the LSD.
    LSD.CYCLES_ACTIVE Cycles Uops delivered by the LSD, but didn't come from the decoder.
    DSB2MITE_SWITCHES.COUNT Number of DSB to MITE switches.
    DSB2MITE_SWITCHES.PENALTY_CYCLES Cycles DSB to MITE switches caused delay.
    DSB_FILL.EXCEED_DSB_LINES DSB Fill encountered > 3 DSB lines.
    ITLB.ITLB_FLUSH Counts the number of ITLB flushes, includes 4k/2M/4M pages.
    OFFCORE_REQUESTS.DEMAND_DATA_RD Demand data read requests sent to uncore.
    OFFCORE_REQUESTS.DEMAND_CODE_RD Demand code read requests sent to uncore.
    OFFCORE_REQUESTS.DEMAND_RFO Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.
    OFFCORE_REQUESTS.ALL_DATA_RD Data read requests sent to uncore (demand and prefetch).
    OFFCORE_REQUESTS.ALL_REQUESTS Any memory transaction that reached the SQ. This includes requests initiated by the core, include all LLC prefetches, page walks, etc.
    UOPS_EXECUTED.THREAD Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.
    UOPS_EXECUTED.CORE Counts total number of uops to be executed per-core each cycle.
    UOPS_EXECUTED.STALL_CYCLES Counts number of cycles no uops were dispatched to be executed on this thread.
    OFFCORE_REQUESTS_BUFFER.SQ_FULL Cases when offcore requests buffer cannot take more entries for core.
    TLB_FLUSH.DTLB_THREAD DTLB flush attempts of the thread-specific entries.
    TLB_FLUSH.STLB_ANY Count number of STLB flush attempts.
    PAGE_WALKS.LLC_MISS Number of any page walk that had a miss in LLC.
    INST_RETIRED.ANY_P Number of instructions at retirement.
    INST_RETIRED.PREC_DIST Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.
    OTHER_ASSISTS.AVX_STORE Number of assists associated with 256-bit AVX store operations.
    OTHER_ASSISTS.AVX_TO_SSE Number of transitions from AVX-256 to legacy SSE when penalty applicable.
    OTHER_ASSISTS.SSE_TO_AVX Number of transitions from SSE to AVX-256 when penalty applicable.
    OTHER_ASSISTS.ANY_WB_ASSIST Number of times any microcode assist is invoked by HW upon uop writeback.
    UOPS_RETIRED.ALL Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles.
    UOPS_RETIRED.RETIRE_SLOTS Counts the number of retirement slots used each cycle.
    UOPS_RETIRED.ALL_PS Retired uops.
    UOPS_RETIRED.STALL_CYCLES Cycles without actually retired uops.
    UOPS_RETIRED.TOTAL_CYCLES Cycles with less than 10 actually retired uops.
    UOPS_RETIRED.RETIRE_SLOTS_PS Retirement slots used.
    UOPS_RETIRED.CORE_STALL_CYCLES Cycles without actually retired uops.
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of machine clears due to memory order conflicts.
    MACHINE_CLEARS.SMC Number of self-modifying-code machine clears detected.
    MACHINE_CLEARS.MASKMOV Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
    BR_INST_RETIRED.CONDITIONAL Counts the number of conditional branch instructions retired.
    BR_INST_RETIRED.NEAR_CALL Direct and indirect near call instructions retired.
    BR_INST_RETIRED.ALL_BRANCHES Branch instructions at retirement.
    BR_INST_RETIRED.NEAR_RETURN Counts the number of near return instructions retired.
    BR_INST_RETIRED.NOT_TAKEN Counts the number of not taken branch instructions retired.
    BR_INST_RETIRED.NEAR_TAKEN Number of near taken branches retired.
    BR_INST_RETIRED.FAR_BRANCH Number of far branches retired.
    BR_INST_RETIRED.CONDITIONAL_PS Conditional branch instructions retired.
    BR_INST_RETIRED.NEAR_CALL_PS Direct and indirect near call instructions retired.
    BR_INST_RETIRED.ALL_BRANCHES_PS All (macro) branch instructions retired.
    BR_INST_RETIRED.NEAR_RETURN_PS Return instructions retired.
    BR_INST_RETIRED.NEAR_TAKEN_PS Taken branch instructions retired.
    BR_INST_RETIRED.NEAR_CALL_R3 Direct and indirect macro near call instructions retired (captured in ring 3).
    BR_INST_RETIRED.NEAR_CALL_R3_PS Direct and indirect macro near call instructions retired (captured in ring 3).
    BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional branch instructions retired.
    BR_MISP_RETIRED.ALL_BRANCHES Mispredicted branch instructions at retirement.
    BR_MISP_RETIRED.NEAR_TAKEN Mispredicted taken branch instructions retired.
    BR_MISP_RETIRED.CONDITIONAL_PS Mispredicted conditional branch instructions retired.
    BR_MISP_RETIRED.ALL_BRANCHES_PS Mispredicted macro branch instructions retired.
    BR_MISP_RETIRED.NEAR_TAKEN_PS number of near branch instructions retired that were mispredicted and taken.
    FP_ASSIST.X87_OUTPUT Number of X87 FP assists due to output values.
    FP_ASSIST.X87_INPUT Number of X87 FP assists due to input values.
    FP_ASSIST.SIMD_OUTPUT Number of SIMD FP assists due to output values.
    FP_ASSIST.SIMD_INPUT Number of SIMD FP assists due to input values.
    FP_ASSIST.ANY Cycles with any input/output SSE* or FP assists.
    ROB_MISC_EVENTS.LBR_INSERTS Count cases of saving new LBR records by hardware.
    MEM_TRANS_RETIRED.PRECISE_STORE Sample stores and collect precise store operation via PEBS record. PMC3 only.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Randomly selected loads with latency value being above 4.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Randomly selected loads with latency value being above 8.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Randomly selected loads with latency value being above 16.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Randomly selected loads with latency value being above 32.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Randomly selected loads with latency value being above 64.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Randomly selected loads with latency value being above 128.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Randomly selected loads with latency value being above 256.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Randomly selected loads with latency value being above 512.
    MEM_UOPS_RETIRED.STLB_MISS_LOADS Retired load uops that miss the STLB.
    MEM_UOPS_RETIRED.STLB_MISS_STORES Retired store uops that miss the STLB.
    MEM_UOPS_RETIRED.LOCK_LOADS Retired load uops with locked access.
    MEM_UOPS_RETIRED.SPLIT_LOADS Retired load uops that split across a cacheline boundary.
    MEM_UOPS_RETIRED.SPLIT_STORES Retired store uops that split across a cacheline boundary.
    MEM_UOPS_RETIRED.ALL_LOADS All retired load uops.
    MEM_UOPS_RETIRED.ALL_STORES All retired store uops.
    MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS Retired load uops that miss the STLB. (Precise Event)
    MEM_UOPS_RETIRED.STLB_MISS_STORES_PS Retired store uops that miss the STLB. (Precise Event)
    MEM_UOPS_RETIRED.LOCK_LOADS_PS Retired load uops with locked access. (Precise Event)
    MEM_UOPS_RETIRED.SPLIT_LOADS_PS Retired load uops that split across a cacheline boundary. (Precise Event)
    MEM_UOPS_RETIRED.SPLIT_STORES_PS Retired store uops that split across a cacheline boundary. (Precise Event)
    MEM_UOPS_RETIRED.ALL_LOADS_PS All retired load uops. (Precise Event)
    MEM_UOPS_RETIRED.ALL_STORES_PS All retired store uops. (Precise Event)
    MEM_LOAD_UOPS_RETIRED.L1_HIT Retired load uops with L1 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.L2_HIT Retired load uops with L2 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.LLC_HIT Retired load uops whose data source was LLC hit with no snoop required.
    MEM_LOAD_UOPS_RETIRED.L1_MISS Retired load uops whose data source followed an L1 miss.
    MEM_LOAD_UOPS_RETIRED.L2_MISS Retired load uops that missed L2, excluding unknown sources.
    MEM_LOAD_UOPS_RETIRED.LLC_MISS Retired load uops whose data source is LLC miss.
    MEM_LOAD_UOPS_RETIRED.HIT_LFB Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
    MEM_LOAD_UOPS_RETIRED.L1_HIT_PS Retired load uops with L1 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.L2_HIT_PS Retired load uops with L2 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS Retired load uops which data sources were data hits in LLC without snoops required.
    MEM_LOAD_UOPS_RETIRED.L1_MISS_PS Retired load uops which data sources following L1 data-cache miss.
    MEM_LOAD_UOPS_RETIRED.L2_MISS_PS Retired load uops with L2 cache misses as data sources.
    MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS Miss in last-level (L3) cache. Excludes Unknown data-source.
    MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM Retired load uops whose data source was an on-package core cache with HitM responses.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE Retired load uops whose data source was LLC hit with no snoop required.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS Retired load uops which data sources were HitM responses from shared LLC.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE_PS Retired load uops which data sources were hits in LLC without snoops required.
    BACLEARS.ANY Number of front end re-steers due to BPU misprediction.
    L2_TRANS.DEMAND_DATA_RD Demand Data Read requests that access L2 cache.
    L2_TRANS.RFO RFO requests that access L2 cache.
    L2_TRANS.CODE_RD L2 cache accesses when fetching instructions.
    L2_TRANS.ALL_PF Any MLC or LLC HW prefetch accessing L2, including rejects.
    L2_TRANS.L1D_WB L1D writebacks that access L2 cache.
    L2_TRANS.L2_FILL L2 fill requests that access L2 cache.
    L2_TRANS.L2_WB L2 writebacks that access L2 cache.
    L2_TRANS.ALL_REQUESTS Transactions accessing L2 pipe.
    L2_LINES_IN.I L2 cache lines in I state filling L2.
    L2_LINES_IN.S L2 cache lines in S state filling L2.
    L2_LINES_IN.E L2 cache lines in E state filling L2.
    L2_LINES_IN.ALL L2 cache lines filling L2.
    L2_LINES_OUT.DEMAND_CLEAN Clean L2 cache lines evicted by demand.
    L2_LINES_OUT.DEMAND_DIRTY Dirty L2 cache lines evicted by demand.
    L2_LINES_OUT.PF_CLEAN Clean L2 cache lines evicted by the MLC prefetcher.
    L2_LINES_OUT.PF_DIRTY Dirty L2 cache lines evicted by the MLC prefetcher.
    L2_LINES_OUT.DIRTY_ALL Dirty L2 cache lines filling the L2.
    SQ_MISC.SPLIT_LOCK Split locks in SQ
    UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC Cycles where at least 1 uop was executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC Cycles where at least 2 uops were executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC Cycles where at least 3 uops were executed per-thread.
    UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC Cycles where at least 4 uops were executed per-thread.
    DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK Misses in all TLB levels that cause a page walk of any page size from demand loads.
    DTLB_LOAD_MISSES.WALK_COMPLETED Misses in all TLB levels that caused page walk completed of any size by demand loads.
    DTLB_LOAD_MISSES.WALK_DURATION Cycle PMH is busy with a walk due to demand loads.
    RS_EVENTS.EMPTY_END Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
    MACHINE_CLEARS.COUNT Number of machine clears (nukes) of any type.
    LSD.CYCLES_4_UOPS Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
    MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).
    IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
    CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss load* is outstanding.
    CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an outstanding load.
    CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls.
    CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding.
    CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss load* is outstanding.
    CYCLE_ACTIVITY.STALLS_MEM_ANY Execution stalls while memory subsystem has an outstanding load.
    CPU_CLK_UNHALTED.THREAD_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CPU_CLK_UNHALTED.THREAD_P_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)
    INT_MISC.RECOVERY_CYCLES_ANY Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
    UOPS_EXECUTED.CORE_CYCLES_GE_1 Cycles at least 1 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_2 Cycles at least 2 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_3 Cycles at least 3 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_4 Cycles at least 4 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_NONE Cycles with no micro-ops executed from any thread on physical core.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
    L1D_PEND_MISS.PENDING_CYCLES_ANY Cycles with L1D load Misses outstanding from any thread on physical core.
    L1D_PEND_MISS.FB_FULL Cycles a demand request was blocked due to Fill Buffers inavailability.
    CPU_CLK_UNHALTED.REF_XCLK Reference cycles when the thread is unhalted. (counts at 100 MHz rate)
    CPU_CLK_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)
    CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other thread is halted.
    UNC_ARB_TRK_OCCUPANCY.ALL Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.
    UNC_ARB_TRK_REQUESTS.ALL Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.
    UNC_ARB_TRK_REQUESTS.WRITES Counts the number of allocated write entries, include full, partial, and LLC evictions.
    UNC_ARB_TRK_REQUESTS.EVICTIONS Counts the number of LLC evictions allocated.
    UNC_ARB_COH_TRK_OCCUPANCY.ALL Cycles weighted by number of requests pending in Coherency Tracker.
    UNC_ARB_COH_TRK_REQUESTS.ALL Number of requests allocated in Coherency Tracker.
    UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
    UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
    UNC_CLOCK.SOCKET This 48-bit fixed counter counts the UCLK cycles.
    UNC_CBO_CACHE_LOOKUP.READ_M L3 Lookup read request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_M L3 Lookup write request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_M L3 Lookup external snoop request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.ANY_M L3 Lookup any request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.READ_I L3 Lookup read request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_I L3 Lookup write request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_I L3 Lookup external snoop request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.ANY_I L3 Lookup any request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.READ_MESI L3 Lookup read request that access cache and found line in any MESI-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_MESI L3 Lookup write request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI L3 Lookup external snoop request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.ANY_MESI L3 Lookup any request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.ANY_ES L3 Lookup any request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_ES L3 Lookup external snoop request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.READ_ES L3 Lookup read request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_ES L3 Lookup write request that access cache and found line in E or S-state.
    UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL An external snoop misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_EVICTION A cross-core snoop resulted from L3 Eviction which misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL An external snoop hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_EVICTION A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL An external snoop hits a modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_EVICTION A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.