Intel® Microarchitecture Code Named Sandy Bridge Events

This section provides reference for hardware events that can be monitored for the CPU(s):

  • Intel® Core™ processor 2xxx Series
  • EventName Description
    INST_RETIRED.ANY This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.
    CPU_CLK_UNHALTED.THREAD This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
    CPU_CLK_UNHALTED.REF_TSC This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
    BR_INST_EXEC.NONTAKEN_CONDITIONAL Not taken macro-conditional branches.
    BR_INST_EXEC.TAKEN_CONDITIONAL Taken speculative and retired macro-conditional branches.
    BR_INST_EXEC.TAKEN_DIRECT_JUMP Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.
    BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired indirect branches excluding calls and returns.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN Taken speculative and retired indirect branches with return mnemonic.
    BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL Taken speculative and retired direct near calls.
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired indirect calls.
    BR_INST_EXEC.ALL_CONDITIONAL Speculative and retired macro-conditional branches.
    BR_INST_EXEC.ALL_DIRECT_JMP Speculative and retired macro-unconditional branches excluding calls and indirects.
    BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Speculative and retired indirect branches excluding calls and returns.
    BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN Speculative and retired indirect return branches.
    BR_INST_EXEC.ALL_DIRECT_NEAR_CALL Speculative and retired direct near calls.
    BR_MISP_EXEC.NONTAKEN_CONDITIONAL Not taken speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.TAKEN_CONDITIONAL Taken speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.TAKEN_RETURN_NEAR Taken speculative and retired mispredicted indirect branches with return mnemonic.
    BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL Taken speculative and retired mispredicted direct near calls.
    BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired mispredicted indirect calls.
    BR_MISP_EXEC.ALL_CONDITIONAL Speculative and retired mispredicted macro conditional branches.
    BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Mispredicted indirect branches excluding calls and returns.
    BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL Speculative and retired mispredicted direct near calls.
    CPU_CLK_UNHALTED.THREAD_P Thread cycles when thread is not in halt state.
    ITLB.ITLB_FLUSH Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
    ICACHE.HIT Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.
    ICACHE.MISSES This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.
    LSD.UOPS Number of Uops delivered by the LSD.
    LSD.CYCLES_ACTIVE Cycles Uops delivered by the LSD, but didn't come from the decoder.
    ILD_STALL.LCP Stalls caused by changing prefix length of the instruction.
    ILD_STALL.IQ_FULL Stall cycles because IQ is full.
    INSTS_WRITTEN_TO_IQ.INSTS Valid instructions written to IQ per cycle.
    IDQ.EMPTY Instruction Decode Queue (IDQ) empty cycles.
    IDQ.MITE_UOPS Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
    IDQ.DSB_UOPS Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.
    IDQ.MS_DSB_UOPS Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MS_MITE_UOPS Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MS_UOPS Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MS_CYCLES This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more information.
    IDQ_UOPS_NOT_DELIVERED.CORE This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
    DSB2MITE_SWITCHES.COUNT Decode Stream Buffer (DSB)-to-MITE switches.
    DSB2MITE_SWITCHES.PENALTY_CYCLES This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.
    DSB_FILL.OTHER_CANCEL Cases of cancelling valid DSB fill not because of exceeding way limit.
    DSB_FILL.EXCEED_DSB_LINES Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.
    INT_MISC.RAT_STALL_CYCLES Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.
    PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP Increments the number of flags-merge uops in flight each cycle.
    PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.
    PARTIAL_RAT_STALLS.MUL_SINGLE_UOP Multiply packed/scalar single precision uops allocated.
    RESOURCE_STALLS.ANY Resource-related stall cycles.
    RESOURCE_STALLS.LB Counts the cycles of stall due to lack of load buffers.
    RESOURCE_STALLS.RS Cycles stalled due to no eligible RS entry available.
    RESOURCE_STALLS.SB Cycles stalled due to no store buffers available. (not including draining form sync).
    RESOURCE_STALLS.ROB Cycles stalled due to re-order buffer full.
    RESOURCE_STALLS2.BOB_FULL Cycles when Allocator is stalled if BOB is full and new branch needs it.
    UOPS_ISSUED.ANY This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.
    UOPS_ISSUED.STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.
    UOPS_ISSUED.CORE_STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.
    RS_EVENTS.EMPTY_CYCLES Cycles when Reservation Station (RS) is empty for the thread.
    CPL_CYCLES.RING0 Unhalted core cycles when the thread is in ring 0.
    CPL_CYCLES.RING0_TRANS Number of intervals between processor halts while thread is in ring 0.
    CPL_CYCLES.RING123 Unhalted core cycles when thread is in rings 1, 2, or 3.
    ROB_MISC_EVENTS.LBR_INSERTS Count cases of saving new LBR.
    MACHINE_CLEARS.MEMORY_ORDERING This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.
    MACHINE_CLEARS.SMC This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.
    MACHINE_CLEARS.MASKMOV Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.
    INST_RETIRED.ANY_P Number of instructions retired. General Counter - architectural event.
    UOPS_RETIRED.ALL This event counts the number of micro-ops retired.
    UOPS_RETIRED.RETIRE_SLOTS This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.
    UOPS_RETIRED.ALL_PS This event counts the number of micro-ops retired. (Precise Event)
    UOPS_RETIRED.STALL_CYCLES Cycles without actually retired uops.
    UOPS_RETIRED.TOTAL_CYCLES Cycles with less than 10 actually retired uops.
    UOPS_RETIRED.RETIRE_SLOTS_PS This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)
    BR_INST_RETIRED.CONDITIONAL Conditional branch instructions retired.
    BR_INST_RETIRED.NEAR_CALL Direct and indirect near call instructions retired.
    BR_INST_RETIRED.ALL_BRANCHES All (macro) branch instructions retired.
    BR_INST_RETIRED.NEAR_RETURN Return instructions retired.
    BR_INST_RETIRED.NOT_TAKEN Not taken branch instructions retired.
    BR_INST_RETIRED.NEAR_TAKEN Taken branch instructions retired.
    BR_INST_RETIRED.FAR_BRANCH Far branch instructions retired.
    BR_INST_RETIRED.CONDITIONAL_PS Conditional branch instructions retired. (Precise Event - PEBS).
    BR_INST_RETIRED.NEAR_CALL_PS Direct and indirect near call instructions retired. (Precise Event - PEBS).
    BR_INST_RETIRED.ALL_BRANCHES_PS All (macro) branch instructions retired. (Precise Event - PEBS).
    BR_INST_RETIRED.NEAR_RETURN_PS Return instructions retired. (Precise Event - PEBS).
    BR_INST_RETIRED.NEAR_TAKEN_PS Taken branch instructions retired. (Precise Event - PEBS).
    BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional branch instructions retired.
    BR_MISP_RETIRED.NEAR_CALL Direct and indirect mispredicted near call instructions retired.
    BR_MISP_RETIRED.ALL_BRANCHES All mispredicted macro branch instructions retired.
    BR_MISP_RETIRED.NOT_TAKEN Mispredicted not taken branch instructions retired.
    BR_MISP_RETIRED.TAKEN Mispredicted taken branch instructions retired.
    BR_MISP_RETIRED.CONDITIONAL_PS Mispredicted conditional branch instructions retired. (Precise Event - PEBS).
    BR_MISP_RETIRED.NEAR_CALL_PS Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).
    BR_MISP_RETIRED.ALL_BRANCHES_PS Mispredicted macro branch instructions retired. (Precise Event - PEBS)
    BR_MISP_RETIRED.NOT_TAKEN_PS Mispredicted not taken branch instructions retired.(Precise Event - PEBS).
    BR_MISP_RETIRED.TAKEN_PS Mispredicted taken branch instructions retired. (Precise Event - PEBS).
    OTHER_ASSISTS.ITLB_MISS_RETIRED Retired instructions experiencing ITLB misses.
    OTHER_ASSISTS.AVX_STORE Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.
    OTHER_ASSISTS.AVX_TO_SSE Number of transitions from AVX-256 to legacy SSE when penalty applicable.
    OTHER_ASSISTS.SSE_TO_AVX Number of transitions from SSE to AVX-256 when penalty applicable.
    FP_ASSIST.X87_OUTPUT Number of X87 assists due to output value.
    FP_ASSIST.X87_INPUT Number of X87 assists due to input value.
    FP_ASSIST.SIMD_OUTPUT Number of SIMD FP assists due to Output values.
    FP_ASSIST.SIMD_INPUT Number of SIMD FP assists due to input values.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Randomly selected loads with latency value being above 4 .
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Randomly selected loads with latency value being above 8.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Randomly selected loads with latency value being above 16.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Randomly selected loads with latency value being above 32.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Randomly selected loads with latency value being above 64.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Randomly selected loads with latency value being above 128.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Randomly selected loads with latency value being above 256.
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Randomly selected loads with latency value being above 512.
    MEM_TRANS_RETIRED.PRECISE_STORE Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).
    MEM_UOPS_RETIRED.STLB_MISS_LOADS Retired load uops that miss the STLB.
    MEM_UOPS_RETIRED.STLB_MISS_STORES Retired store uops that miss the STLB.
    MEM_UOPS_RETIRED.LOCK_LOADS Retired load uops with locked access.
    MEM_UOPS_RETIRED.SPLIT_LOADS This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.SPLIT_STORES This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
    MEM_UOPS_RETIRED.ALL_LOADS This event counts the number of load uops retired
    MEM_UOPS_RETIRED.ALL_STORES This event counts the number of store uops retired.
    MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS Retired load uops that miss the STLB. (Precise Event - PEBS).
    MEM_UOPS_RETIRED.STLB_MISS_STORES_PS Retired store uops that miss the STLB. (Precise Event - PEBS).
    MEM_UOPS_RETIRED.LOCK_LOADS_PS Retired load uops with locked access. (Precise Event - PEBS).
    MEM_UOPS_RETIRED.SPLIT_LOADS_PS This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)
    MEM_UOPS_RETIRED.SPLIT_STORES_PS This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)
    MEM_UOPS_RETIRED.ALL_LOADS_PS This event counts the number of load uops retired (Precise Event)
    MEM_UOPS_RETIRED.ALL_STORES_PS This event counts the number of store uops retired. (Precise Event - PEBS)
    MEM_LOAD_UOPS_RETIRED.L1_HIT Retired load uops with L1 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.L2_HIT Retired load uops with L2 cache hits as data sources.
    MEM_LOAD_UOPS_RETIRED.LLC_HIT This event counts retired load uops that hit in the last-level (L3) cache without snoops required.
    MEM_LOAD_UOPS_RETIRED.HIT_LFB Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
    MEM_LOAD_UOPS_RETIRED.L1_HIT_PS Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).
    MEM_LOAD_UOPS_RETIRED.L2_HIT_PS Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).
    MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS)
    MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE Retired load uops which data sources were hits in LLC without snoops required.
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS)
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS)
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE_PS Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).
    MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops.
    MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS)
    ARITH.FPU_DIV_ACTIVE Cycles when divider is busy executing divide operations.
    ARITH.FPU_DIV This event counts the number of the divide operations executed.
    FP_COMP_OPS_EXE.X87 Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.
    FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_PACKED_SINGLE Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.
    FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.
    SIMD_FP_256.PACKED_SINGLE Number of GSSE-256 Computational FP single precision uops issued this cycle.
    SIMD_FP_256.PACKED_DOUBLE Number of AVX-256 Computational FP double precision uops issued this cycle.
    UOPS_DISPATCHED.THREAD Uops dispatched per thread.
    UOPS_DISPATCHED.STALL_CYCLES Cases of no uops dispatched per thread.
    UOPS_DISPATCHED.CORE Uops dispatched from any thread.
    UOPS_DISPATCHED_PORT.PORT_0 Cycles per thread when uops are dispatched to port 0.
    UOPS_DISPATCHED_PORT.PORT_1 Cycles per thread when uops are dispatched to port 1.
    UOPS_DISPATCHED_PORT.PORT_4 Cycles per thread when uops are dispatched to port 4.
    UOPS_DISPATCHED_PORT.PORT_5 Cycles per thread when uops are dispatched to port 5.
    CYCLE_ACTIVITY.CYCLES_NO_DISPATCH Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.
    CYCLE_ACTIVITY.CYCLES_L1D_PENDING Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
    CYCLE_ACTIVITY.CYCLES_L2_PENDING Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.
    CYCLE_ACTIVITY.STALLS_L1D_PENDING Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
    CYCLE_ACTIVITY.STALLS_L2_PENDING Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.
    EPT.WALK_CYCLES Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
    ITLB_MISSES.MISS_CAUSES_A_WALK Misses at all ITLB levels that cause page walks.
    ITLB_MISSES.WALK_COMPLETED Misses in all ITLB levels that cause completed page walks.
    ITLB_MISSES.WALK_DURATION This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.
    ITLB_MISSES.STLB_HIT Operations that miss the first ITLB level but hit the second and do not cause any page walks.
    DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK Load misses in all DTLB levels that cause page walks.
    DTLB_LOAD_MISSES.WALK_COMPLETED Load misses at all DTLB levels that cause completed page walks.
    DTLB_LOAD_MISSES.WALK_DURATION This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.
    DTLB_LOAD_MISSES.STLB_HIT This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.
    DTLB_STORE_MISSES.MISS_CAUSES_A_WALK Store misses in all DTLB levels that cause page walks.
    DTLB_STORE_MISSES.WALK_COMPLETED Store misses in all DTLB levels that cause completed page walks.
    DTLB_STORE_MISSES.WALK_DURATION Cycles when PMH is busy with page walks.
    DTLB_STORE_MISSES.STLB_HIT Store operations that miss the first TLB level but hit the second and do not cause page walks.
    TLB_FLUSH.DTLB_THREAD DTLB flush attempts of the thread-specific entries.
    TLB_FLUSH.STLB_ANY STLB flush attempts.
    PAGE_WALKS.LLC_MISS Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.
    L1D.REPLACEMENT This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.
    L1D.ALLOCATED_IN_M Allocated L1D data cache lines in M state.
    L1D.EVICTION L1D data cache lines in M state evicted due to replacement.
    L1D.ALL_M_REPLACEMENT Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.
    L1D_PEND_MISS.PENDING L1D miss oustandings duration in cycles.
    L1D_PEND_MISS.PENDING_CYCLES Cycles with L1D load Misses outstanding.
    LOAD_HIT_PRE.SW_PF Not software-prefetch load dispatches that hit FB allocated for software prefetch.
    LOAD_HIT_PRE.HW_PF Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.
    HW_PRE_REQ.DL1_MISS Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .
    LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION Cycles when L1 and L2 are locked due to UC or split lock.
    LOCK_CYCLES.CACHE_LOCK_DURATION Cycles when L1D is locked.
    LD_BLOCKS.DATA_UNKNOWN Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.
    LD_BLOCKS.STORE_FORWARD This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel® 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.
    LD_BLOCKS.NO_SR This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
    LD_BLOCKS.ALL_BLOCK Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).
    LD_BLOCKS_PARTIAL.ADDRESS_ALIAS Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.
    LD_BLOCKS_PARTIAL.ALL_STA_BLOCK This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
    MISALIGN_MEM_REF.LOADS Speculative cache line split load uops dispatched to L1 cache.
    MISALIGN_MEM_REF.STORES Speculative cache line split STA uops dispatched to L1 cache.
    AGU_BYPASS_CANCEL.COUNT This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD Offcore outstanding Demand Data Read transactions in uncore queue.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.
    OFFCORE_REQUESTS.DEMAND_DATA_RD Demand Data Read requests sent to uncore.
    OFFCORE_REQUESTS.DEMAND_CODE_RD Cacheable and noncachaeble code read requests.
    OFFCORE_REQUESTS.DEMAND_RFO Demand RFO requests including regular RFOs, locks, ItoM.
    OFFCORE_REQUESTS.ALL_DATA_RD Demand and prefetch data reads.
    OFFCORE_REQUESTS_BUFFER.SQ_FULL Cases when offcore requests buffer cannot take more entries for core.
    L2_RQSTS.DEMAND_DATA_RD_HIT Demand Data Read requests that hit L2 cache.
    L2_RQSTS.RFO_HIT RFO requests that hit L2 cache.
    L2_RQSTS.RFO_MISS RFO requests that miss L2 cache.
    L2_RQSTS.CODE_RD_HIT L2 cache hits when fetching instructions, code reads.
    L2_RQSTS.CODE_RD_MISS L2 cache misses when fetching instructions.
    L2_RQSTS.PF_HIT Requests from the L2 hardware prefetchers that hit L2 cache.
    L2_RQSTS.PF_MISS Requests from the L2 hardware prefetchers that miss L2 cache.
    L2_STORE_LOCK_RQSTS.MISS RFOs that miss cache lines.
    L2_STORE_LOCK_RQSTS.HIT_E RFOs that hit cache lines in E state.
    L2_STORE_LOCK_RQSTS.HIT_M RFOs that hit cache lines in M state.
    L2_STORE_LOCK_RQSTS.ALL RFOs that access cache lines in any state.
    L2_L1D_WB_RQSTS.MISS Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).
    L2_L1D_WB_RQSTS.HIT_S Not rejected writebacks from L1D to L2 cache lines in S state.
    L2_L1D_WB_RQSTS.HIT_E Not rejected writebacks from L1D to L2 cache lines in E state.
    L2_L1D_WB_RQSTS.HIT_M Not rejected writebacks from L1D to L2 cache lines in M state.
    L2_L1D_WB_RQSTS.ALL Not rejected writebacks from L1D to L2 cache lines in any state.
    L2_TRANS.DEMAND_DATA_RD Demand Data Read requests that access L2 cache.
    L2_TRANS.RFO RFO requests that access L2 cache.
    L2_TRANS.CODE_RD L2 cache accesses when fetching instructions.
    L2_TRANS.ALL_PF L2 or LLC HW prefetches that access L2 cache.
    L2_TRANS.L1D_WB L1D writebacks that access L2 cache.
    L2_TRANS.L2_FILL L2 fill requests that access L2 cache.
    L2_TRANS.L2_WB L2 writebacks that access L2 cache.
    L2_TRANS.ALL_REQUESTS Transactions accessing L2 pipe.
    L2_LINES_IN.I L2 cache lines in I state filling L2.
    L2_LINES_IN.S L2 cache lines in S state filling L2.
    L2_LINES_IN.E L2 cache lines in E state filling L2.
    L2_LINES_IN.ALL This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.
    L2_LINES_OUT.DEMAND_CLEAN Clean L2 cache lines evicted by demand.
    L2_LINES_OUT.DEMAND_DIRTY Dirty L2 cache lines evicted by demand.
    L2_LINES_OUT.PF_CLEAN Clean L2 cache lines evicted by L2 prefetch.
    L2_LINES_OUT.PF_DIRTY Dirty L2 cache lines evicted by L2 prefetch.
    L2_LINES_OUT.DIRTY_ALL Dirty L2 cache lines filling the L2.
    LONGEST_LAT_CACHE.MISS Core-originated cacheable demand requests missed LLC.
    LONGEST_LAT_CACHE.REFERENCE Core-originated cacheable demand requests that refer to LLC.
    SQ_MISC.SPLIT_LOCK Split locks in SQ.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK Reference cycles when the thread is unhalted (counts at 100 MHz rate).
    CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other is halted.
    BR_INST_RETIRED.NEAR_CALL_R3 Direct and indirect macro near call instructions retired (captured in ring 3).
    BR_INST_RETIRED.NEAR_CALL_R3_PS Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).
    UOPS_DISPATCHED_PORT.PORT_0_CORE Cycles per core when uops are dispatched to port 0.
    UOPS_DISPATCHED_PORT.PORT_1_CORE Cycles per core when uops are dispatched to port 1.
    UOPS_DISPATCHED_PORT.PORT_4_CORE Cycles per core when uops are dispatched to port 4.
    UOPS_DISPATCHED_PORT.PORT_5_CORE Cycles per core when uops are dispatched to port 5.
    IDQ.MITE_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.
    IDQ.DSB_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
    UOPS_DISPATCHED_PORT.PORT_2 Cycles per thread when load or STA uops are dispatched to port 2.
    UOPS_DISPATCHED_PORT.PORT_3 Cycles per thread when load or STA uops are dispatched to port 3.
    IDQ.MS_DSB_CYCLES Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
    IDQ.MS_DSB_OCCUR Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.
    UOPS_DISPATCHED_PORT.PORT_2_CORE Cycles per core when load or STA uops are dispatched to port 2.
    UOPS_DISPATCHED_PORT.PORT_3_CORE Cycles per core when load or STA uops are dispatched to port 3.
    INST_RETIRED.PREC_DIST Instructions retired. (Precise Event - PEBS).
    L2_RQSTS.ALL_DEMAND_DATA_RD Demand Data Read requests.
    L2_RQSTS.ALL_RFO RFO requests to L2 cache.
    L2_RQSTS.ALL_CODE_RD L2 code requests.
    L2_RQSTS.ALL_PF Requests from L2 hardware prefetchers.
    L1D_BLOCKS.BANK_CONFLICT_CYCLES Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.
    RESOURCE_STALLS2.ALL_PRF_CONTROL Resource stalls2 control structures full for physical registers.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE Cycles with less than 2 uops delivered by the front end.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE Cycles with less than 3 uops delivered by the front end.
    RESOURCE_STALLS2.ALL_FL_EMPTY Cycles with either free list is empty.
    RESOURCE_STALLS.MEM_RS Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.
    RESOURCE_STALLS.OOO_RSRC Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.
    RESOURCE_STALLS2.OOO_RSRC Resource stalls out of order resources full.
    RESOURCE_STALLS.LB_SB Resource stalls due to load or store buffers all being in use.
    INT_MISC.RECOVERY_CYCLES Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
    PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE Cycles when 1 or more uops were delivered to the by the front end.
    INT_MISC.RECOVERY_STALLS_COUNT Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
    IDQ.ALL_DSB_CYCLES_4_UOPS Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.
    IDQ.ALL_DSB_CYCLES_ANY_UOPS Cycles Decode Stream Buffer (DSB) is delivering any Uop.
    IDQ.ALL_MITE_CYCLES_4_UOPS Cycles MITE is delivering 4 Uops.
    IDQ.ALL_MITE_CYCLES_ANY_UOPS Cycles MITE is delivering any Uop.
    DSB_FILL.ALL_CANCEL Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.
    FP_ASSIST.ANY Cycles with any input/output SSE or FP assist.
    BACLEARS.ANY Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
    IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
    BR_INST_EXEC.ALL_BRANCHES Speculative and retired branches.
    BR_MISP_EXEC.ALL_BRANCHES Speculative and retired mispredicted macro conditional branches.
    IDQ.MITE_ALL_UOPS Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
    UOPS_RETIRED.CORE_STALL_CYCLES Cycles without actually retired uops.
    LSD.CYCLES_4_UOPS Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
    MACHINE_CLEARS.COUNT Number of machine clears (nukes) of any type.
    RS_EVENTS.EMPTY_END Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
    IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
    CPU_CLK_UNHALTED.THREAD_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CPU_CLK_UNHALTED.THREAD_P_ANY Core cycles when at least one thread on the physical core is not in halt state.
    CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
    INT_MISC.RECOVERY_CYCLES_ANY Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
    UOPS_EXECUTED.CORE_CYCLES_GE_1 Cycles at least 1 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_2 Cycles at least 2 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_3 Cycles at least 3 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_GE_4 Cycles at least 4 micro-op is executed from any thread on physical core.
    UOPS_EXECUTED.CORE_CYCLES_NONE Cycles with no micro-ops executed from any thread on physical core.
    L1D_PEND_MISS.PENDING_CYCLES_ANY Cycles with L1D load Misses outstanding from any thread on physical core.
    L1D_PEND_MISS.FB_FULL Cycles a demand request was blocked due to Fill Buffers inavailability.
    CPU_CLK_UNHALTED.REF_XCLK Reference cycles when the thread is unhalted (counts at 100 MHz rate)
    CPU_CLK_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
    CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other thread is halted.
    UNC_ARB_TRK_OCCUPANCY.ALL Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.
    UNC_ARB_TRK_REQUESTS.ALL Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.
    UNC_ARB_TRK_REQUESTS.WRITES Counts the number of allocated write entries, include full, partial, and LLC evictions.
    UNC_ARB_TRK_REQUESTS.EVICTIONS Counts the number of LLC evictions allocated.
    UNC_ARB_COH_TRK_OCCUPANCY.ALL Cycles weighted by number of requests pending in Coherency Tracker.
    UNC_ARB_COH_TRK_REQUESTS.ALL Number of requests allocated in Coherency Tracker.
    UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
    UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
    UNC_CLOCK.SOCKET This 48-bit fixed counter counts the UCLK cycles.
    UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL An external snoop misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.MISS_EVICTION A cross-core snoop resulted from L3 Eviction which misses in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL An external snoop hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HIT_EVICTION A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL An external snoop hits a modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_XCORE A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.
    UNC_CBO_XSNP_RESPONSE.HITM_EVICTION A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.
    UNC_CBO_CACHE_LOOKUP.READ_M L3 Lookup read request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_M L3 Lookup write request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_M L3 Lookup external snoop request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.ANY_M L3 Lookup any request that access cache and found line in M-state.
    UNC_CBO_CACHE_LOOKUP.READ_I L3 Lookup read request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_I L3 Lookup write request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_I L3 Lookup external snoop request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.ANY_I L3 Lookup any request that access cache and found line in I-state.
    UNC_CBO_CACHE_LOOKUP.READ_MESI L3 Lookup read request that access cache and found line in any MESI-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_MESI L3 Lookup write request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI L3 Lookup external snoop request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.ANY_MESI L3 Lookup any request that access cache and found line in MESI-state.
    UNC_CBO_CACHE_LOOKUP.ANY_ES L3 Lookup any request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.EXTSNP_ES L3 Lookup external snoop request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.READ_ES L3 Lookup read request that access cache and found line in E or S-state.
    UNC_CBO_CACHE_LOOKUP.WRITE_ES L3 Lookup write request that access cache and found line in E or S-state.